imx/svc/pm.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * Copyright (C) 2016 Freescale Semiconductor, Inc.
0004  * Copyright 2017-2018 NXP
0005  *
0006  * Header file containing the public API for the System Controller (SC)
0007  * Power Management (PM) function. This includes functions for power state
0008  * control, clock control, reset control, and wake-up event control.
0009  *
0010  * PM_SVC (SVC) Power Management Service
0011  *
0012  * Module for the Power Management (PM) service.
0013  */
0014
0015 #ifndef _SC_PM_API_H
0016 #define _SC_PM_API_H
0017
0018 #include <linux/firmware/imx/sci.h>
0019
0020 /*
0021  * This type is used to indicate RPC PM function calls.
0022  */
0023 enum imx_sc_pm_func {
0024     IMX_SC_PM_FUNC_UNKNOWN = 0,
0025     IMX_SC_PM_FUNC_SET_SYS_POWER_MODE = 19,
0026     IMX_SC_PM_FUNC_SET_PARTITION_POWER_MODE = 1,
0027     IMX_SC_PM_FUNC_GET_SYS_POWER_MODE = 2,
0028     IMX_SC_PM_FUNC_SET_RESOURCE_POWER_MODE = 3,
0029     IMX_SC_PM_FUNC_GET_RESOURCE_POWER_MODE = 4,
0030     IMX_SC_PM_FUNC_REQ_LOW_POWER_MODE = 16,
0031     IMX_SC_PM_FUNC_SET_CPU_RESUME_ADDR = 17,
0032     IMX_SC_PM_FUNC_REQ_SYS_IF_POWER_MODE = 18,
0033     IMX_SC_PM_FUNC_SET_CLOCK_RATE = 5,
0034     IMX_SC_PM_FUNC_GET_CLOCK_RATE = 6,
0035     IMX_SC_PM_FUNC_CLOCK_ENABLE = 7,
0036     IMX_SC_PM_FUNC_SET_CLOCK_PARENT = 14,
0037     IMX_SC_PM_FUNC_GET_CLOCK_PARENT = 15,
0038     IMX_SC_PM_FUNC_RESET = 13,
0039     IMX_SC_PM_FUNC_RESET_REASON = 10,
0040     IMX_SC_PM_FUNC_BOOT = 8,
0041     IMX_SC_PM_FUNC_REBOOT = 9,
0042     IMX_SC_PM_FUNC_REBOOT_PARTITION = 12,
0043     IMX_SC_PM_FUNC_CPU_START = 11,
0044 };
0045
0046 /*
0047  * Defines for ALL parameters
0048  */
0049 #define IMX_SC_PM_CLK_ALL       UINT8_MAX   /* All clocks */
0050
0051 /*
0052  * Defines for SC PM Power Mode
0053  */
0054 #define IMX_SC_PM_PW_MODE_OFF   0   /* Power off */
0055 #define IMX_SC_PM_PW_MODE_STBY  1   /* Power in standby */
0056 #define IMX_SC_PM_PW_MODE_LP    2   /* Power in low-power */
0057 #define IMX_SC_PM_PW_MODE_ON    3   /* Power on */
0058
0059 /*
0060  * Defines for SC PM CLK
0061  */
0062 #define IMX_SC_PM_CLK_SLV_BUS   0   /* Slave bus clock */
0063 #define IMX_SC_PM_CLK_MST_BUS   1   /* Master bus clock */
0064 #define IMX_SC_PM_CLK_PER   2   /* Peripheral clock */
0065 #define IMX_SC_PM_CLK_PHY   3   /* Phy clock */
0066 #define IMX_SC_PM_CLK_MISC  4   /* Misc clock */
0067 #define IMX_SC_PM_CLK_MISC0 0   /* Misc 0 clock */
0068 #define IMX_SC_PM_CLK_MISC1 1   /* Misc 1 clock */
0069 #define IMX_SC_PM_CLK_MISC2 2   /* Misc 2 clock */
0070 #define IMX_SC_PM_CLK_MISC3 3   /* Misc 3 clock */
0071 #define IMX_SC_PM_CLK_MISC4 4   /* Misc 4 clock */
0072 #define IMX_SC_PM_CLK_CPU   2   /* CPU clock */
0073 #define IMX_SC_PM_CLK_PLL   4   /* PLL */
0074 #define IMX_SC_PM_CLK_BYPASS    4   /* Bypass clock */
0075
0076 /*
0077  * Defines for SC PM CLK Parent
0078  */
0079 #define IMX_SC_PM_PARENT_XTAL   0   /* Parent is XTAL. */
0080 #define IMX_SC_PM_PARENT_PLL0   1   /* Parent is PLL0 */
0081 #define IMX_SC_PM_PARENT_PLL1   2   /* Parent is PLL1 or PLL0/2 */
0082 #define IMX_SC_PM_PARENT_PLL2   3   /* Parent in PLL2 or PLL0/4 */
0083 #define IMX_SC_PM_PARENT_BYPS   4   /* Parent is a bypass clock. */
0084
0085 #endif /* _SC_PM_API_H */