linux/dsa/tag_qca.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002
0003 #ifndef __TAG_QCA_H
0004 #define __TAG_QCA_H
0005
0006 #include <linux/types.h>
0007
0008 struct dsa_switch;
0009 struct sk_buff;
0010
0011 #define QCA_HDR_LEN 2
0012 #define QCA_HDR_VERSION 0x2
0013
0014 #define QCA_HDR_RECV_VERSION        GENMASK(15, 14)
0015 #define QCA_HDR_RECV_PRIORITY       GENMASK(13, 11)
0016 #define QCA_HDR_RECV_TYPE       GENMASK(10, 6)
0017 #define QCA_HDR_RECV_FRAME_IS_TAGGED    BIT(3)
0018 #define QCA_HDR_RECV_SOURCE_PORT    GENMASK(2, 0)
0019
0020 /* Packet type for recv */
0021 #define QCA_HDR_RECV_TYPE_NORMAL    0x0
0022 #define QCA_HDR_RECV_TYPE_MIB       0x1
0023 #define QCA_HDR_RECV_TYPE_RW_REG_ACK    0x2
0024
0025 #define QCA_HDR_XMIT_VERSION        GENMASK(15, 14)
0026 #define QCA_HDR_XMIT_PRIORITY       GENMASK(13, 11)
0027 #define QCA_HDR_XMIT_CONTROL        GENMASK(10, 8)
0028 #define QCA_HDR_XMIT_FROM_CPU       BIT(7)
0029 #define QCA_HDR_XMIT_DP_BIT     GENMASK(6, 0)
0030
0031 /* Packet type for xmit */
0032 #define QCA_HDR_XMIT_TYPE_NORMAL    0x0
0033 #define QCA_HDR_XMIT_TYPE_RW_REG    0x1
0034
0035 /* Check code for a valid mgmt packet. Switch will ignore the packet
0036  * with this wrong.
0037  */
0038 #define QCA_HDR_MGMT_CHECK_CODE_VAL 0x5
0039
0040 /* Specific define for in-band MDIO read/write with Ethernet packet */
0041 #define QCA_HDR_MGMT_SEQ_LEN        4 /* 4 byte for the seq */
0042 #define QCA_HDR_MGMT_COMMAND_LEN    4 /* 4 byte for the command */
0043 #define QCA_HDR_MGMT_DATA1_LEN      4 /* First 4 byte for the mdio data */
0044 #define QCA_HDR_MGMT_HEADER_LEN     (QCA_HDR_MGMT_SEQ_LEN + \
0045                     QCA_HDR_MGMT_COMMAND_LEN + \
0046                     QCA_HDR_MGMT_DATA1_LEN)
0047
0048 #define QCA_HDR_MGMT_DATA2_LEN      12 /* Other 12 byte for the mdio data */
0049 #define QCA_HDR_MGMT_PADDING_LEN    34 /* Padding to reach the min Ethernet packet */
0050
0051 #define QCA_HDR_MGMT_PKT_LEN        (QCA_HDR_MGMT_HEADER_LEN + \
0052                     QCA_HDR_LEN + \
0053                     QCA_HDR_MGMT_DATA2_LEN + \
0054                     QCA_HDR_MGMT_PADDING_LEN)
0055
0056 #define QCA_HDR_MGMT_SEQ_NUM        GENMASK(31, 0)  /* 63, 32 */
0057 #define QCA_HDR_MGMT_CHECK_CODE     GENMASK(31, 29) /* 31, 29 */
0058 #define QCA_HDR_MGMT_CMD        BIT(28)     /* 28 */
0059 #define QCA_HDR_MGMT_LENGTH     GENMASK(23, 20) /* 23, 20 */
0060 #define QCA_HDR_MGMT_ADDR       GENMASK(18, 0)  /* 18, 0 */
0061
0062 /* Special struct emulating a Ethernet header */
0063 struct qca_mgmt_ethhdr {
0064     u32 command;        /* command bit 31:0 */
0065     u32 seq;        /* seq 63:32 */
0066     u32 mdio_data;      /* first 4byte mdio */
0067     __be16 hdr;     /* qca hdr */
0068 } __packed;
0069
0070 enum mdio_cmd {
0071     MDIO_WRITE = 0x0,
0072     MDIO_READ
0073 };
0074
0075 struct mib_ethhdr {
0076     u32 data[3];        /* first 3 mib counter */
0077     __be16 hdr;     /* qca hdr */
0078 } __packed;
0079
0080 struct qca_tagger_data {
0081     void (*rw_reg_ack_handler)(struct dsa_switch *ds,
0082                    struct sk_buff *skb);
0083     void (*mib_autocast_handler)(struct dsa_switch *ds,
0084                      struct sk_buff *skb);
0085 };
0086
0087 #endif /* __TAG_QCA_H */