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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */ 0002 /* 0003 * Xilinx DMA Engine drivers support header file 0004 * 0005 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved. 0006 */ 0007 0008 #ifndef __DMA_XILINX_DMA_H 0009 #define __DMA_XILINX_DMA_H 0010 0011 #include <linux/dma-mapping.h> 0012 #include <linux/dmaengine.h> 0013 0014 /** 0015 * struct xilinx_vdma_config - VDMA Configuration structure 0016 * @frm_dly: Frame delay 0017 * @gen_lock: Whether in gen-lock mode 0018 * @master: Master that it syncs to 0019 * @frm_cnt_en: Enable frame count enable 0020 * @park: Whether wants to park 0021 * @park_frm: Frame to park on 0022 * @coalesc: Interrupt coalescing threshold 0023 * @delay: Delay counter 0024 * @reset: Reset Channel 0025 * @ext_fsync: External Frame Sync source 0026 * @vflip_en: Vertical Flip enable 0027 */ 0028 struct xilinx_vdma_config { 0029 int frm_dly; 0030 int gen_lock; 0031 int master; 0032 int frm_cnt_en; 0033 int park; 0034 int park_frm; 0035 int coalesc; 0036 int delay; 0037 int reset; 0038 int ext_fsync; 0039 bool vflip_en; 0040 }; 0041 0042 int xilinx_vdma_channel_set_config(struct dma_chan *dchan, 0043 struct xilinx_vdma_config *cfg); 0044 0045 #endif
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