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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * CPPI5 descriptors interface
0004  *
0005  * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
0006  */
0007 
0008 #ifndef __TI_CPPI5_H__
0009 #define __TI_CPPI5_H__
0010 
0011 #include <linux/bitops.h>
0012 #include <linux/printk.h>
0013 #include <linux/bug.h>
0014 
0015 /**
0016  * struct cppi5_desc_hdr_t - Descriptor header, present in all types of
0017  *               descriptors
0018  * @pkt_info0:      Packet info word 0 (n/a in Buffer desc)
0019  * @pkt_info0:      Packet info word 1 (n/a in Buffer desc)
0020  * @pkt_info0:      Packet info word 2 (n/a in Buffer desc)
0021  * @src_dst_tag:    Packet info word 3 (n/a in Buffer desc)
0022  */
0023 struct cppi5_desc_hdr_t {
0024     u32 pkt_info0;
0025     u32 pkt_info1;
0026     u32 pkt_info2;
0027     u32 src_dst_tag;
0028 } __packed;
0029 
0030 /**
0031  * struct cppi5_host_desc_t - Host-mode packet and buffer descriptor definition
0032  * @hdr:        Descriptor header
0033  * @next_desc:      word 4/5: Linking word
0034  * @buf_ptr:        word 6/7: Buffer pointer
0035  * @buf_info1:      word 8: Buffer valid data length
0036  * @org_buf_len:    word 9: Original buffer length
0037  * @org_buf_ptr:    word 10/11: Original buffer pointer
0038  * @epib[0]:        Extended Packet Info Data (optional, 4 words), and/or
0039  *          Protocol Specific Data (optional, 0-128 bytes in
0040  *          multiples of 4), and/or
0041  *          Other Software Data (0-N bytes, optional)
0042  */
0043 struct cppi5_host_desc_t {
0044     struct cppi5_desc_hdr_t hdr;
0045     u64 next_desc;
0046     u64 buf_ptr;
0047     u32 buf_info1;
0048     u32 org_buf_len;
0049     u64 org_buf_ptr;
0050     u32 epib[];
0051 } __packed;
0052 
0053 #define CPPI5_DESC_MIN_ALIGN            (16U)
0054 
0055 #define CPPI5_INFO0_HDESC_EPIB_SIZE     (16U)
0056 #define CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE   (128U)
0057 
0058 #define CPPI5_INFO0_HDESC_TYPE_SHIFT        (30U)
0059 #define CPPI5_INFO0_HDESC_TYPE_MASK     GENMASK(31, 30)
0060 #define   CPPI5_INFO0_DESC_TYPE_VAL_HOST    (1U)
0061 #define   CPPI5_INFO0_DESC_TYPE_VAL_MONO    (2U)
0062 #define   CPPI5_INFO0_DESC_TYPE_VAL_TR      (3U)
0063 #define CPPI5_INFO0_HDESC_EPIB_PRESENT      BIT(29)
0064 /*
0065  * Protocol Specific Words location:
0066  * 0 - located in the descriptor,
0067  * 1 = located in the SOP Buffer immediately prior to the data.
0068  */
0069 #define CPPI5_INFO0_HDESC_PSINFO_LOCATION   BIT(28)
0070 #define CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT (22U)
0071 #define CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK  GENMASK(27, 22)
0072 #define CPPI5_INFO0_HDESC_PKTLEN_SHIFT      (0)
0073 #define CPPI5_INFO0_HDESC_PKTLEN_MASK       GENMASK(21, 0)
0074 
0075 #define CPPI5_INFO1_DESC_PKTERROR_SHIFT     (28U)
0076 #define CPPI5_INFO1_DESC_PKTERROR_MASK      GENMASK(31, 28)
0077 #define CPPI5_INFO1_HDESC_PSFLGS_SHIFT      (24U)
0078 #define CPPI5_INFO1_HDESC_PSFLGS_MASK       GENMASK(27, 24)
0079 #define CPPI5_INFO1_DESC_PKTID_SHIFT        (14U)
0080 #define CPPI5_INFO1_DESC_PKTID_MASK     GENMASK(23, 14)
0081 #define CPPI5_INFO1_DESC_FLOWID_SHIFT       (0)
0082 #define CPPI5_INFO1_DESC_FLOWID_MASK        GENMASK(13, 0)
0083 #define CPPI5_INFO1_DESC_FLOWID_DEFAULT     CPPI5_INFO1_DESC_FLOWID_MASK
0084 
0085 #define CPPI5_INFO2_HDESC_PKTTYPE_SHIFT     (27U)
0086 #define CPPI5_INFO2_HDESC_PKTTYPE_MASK      GENMASK(31, 27)
0087 /* Return Policy: 0 - Entire packet 1 - Each buffer */
0088 #define CPPI5_INFO2_HDESC_RETPOLICY     BIT(18)
0089 /*
0090  * Early Return:
0091  * 0 = desc pointers should be returned after all reads have been completed
0092  * 1 = desc pointers should be returned immediately upon fetching
0093  * the descriptor and beginning to transfer data.
0094  */
0095 #define CPPI5_INFO2_HDESC_EARLYRET      BIT(17)
0096 /*
0097  * Return Push Policy:
0098  * 0 = Descriptor must be returned to tail of queue
0099  * 1 = Descriptor must be returned to head of queue
0100  */
0101 #define CPPI5_INFO2_DESC_RETPUSHPOLICY      BIT(16)
0102 #define CPPI5_INFO2_DESC_RETP_MASK      GENMASK(18, 16)
0103 
0104 #define CPPI5_INFO2_DESC_RETQ_SHIFT     (0)
0105 #define CPPI5_INFO2_DESC_RETQ_MASK      GENMASK(15, 0)
0106 
0107 #define CPPI5_INFO3_DESC_SRCTAG_SHIFT       (16U)
0108 #define CPPI5_INFO3_DESC_SRCTAG_MASK        GENMASK(31, 16)
0109 #define CPPI5_INFO3_DESC_DSTTAG_SHIFT       (0)
0110 #define CPPI5_INFO3_DESC_DSTTAG_MASK        GENMASK(15, 0)
0111 
0112 #define CPPI5_BUFINFO1_HDESC_DATA_LEN_SHIFT (0)
0113 #define CPPI5_BUFINFO1_HDESC_DATA_LEN_MASK  GENMASK(27, 0)
0114 
0115 #define CPPI5_OBUFINFO0_HDESC_BUF_LEN_SHIFT (0)
0116 #define CPPI5_OBUFINFO0_HDESC_BUF_LEN_MASK  GENMASK(27, 0)
0117 
0118 /**
0119  * struct cppi5_desc_epib_t - Host Packet Descriptor Extended Packet Info Block
0120  * @timestamp:      word 0: application specific timestamp
0121  * @sw_info0:       word 1: Software Info 0
0122  * @sw_info1:       word 1: Software Info 1
0123  * @sw_info2:       word 1: Software Info 2
0124  */
0125 struct cppi5_desc_epib_t {
0126     u32 timestamp;  /* w0: application specific timestamp */
0127     u32 sw_info0;   /* w1: Software Info 0 */
0128     u32 sw_info1;   /* w2: Software Info 1 */
0129     u32 sw_info2;   /* w3: Software Info 2 */
0130 };
0131 
0132 /**
0133  * struct cppi5_monolithic_desc_t - Monolithic-mode packet descriptor
0134  * @hdr:        Descriptor header
0135  * @epib[0]:        Extended Packet Info Data (optional, 4 words), and/or
0136  *          Protocol Specific Data (optional, 0-128 bytes in
0137  *          multiples of 4), and/or
0138  *          Other Software Data (0-N bytes, optional)
0139  */
0140 struct cppi5_monolithic_desc_t {
0141     struct cppi5_desc_hdr_t hdr;
0142     u32 epib[];
0143 };
0144 
0145 #define CPPI5_INFO2_MDESC_DATA_OFFSET_SHIFT (18U)
0146 #define CPPI5_INFO2_MDESC_DATA_OFFSET_MASK  GENMASK(26, 18)
0147 
0148 /*
0149  * Reload Count:
0150  * 0 = Finish the packet and place the descriptor back on the return queue
0151  * 1-0x1ff = Vector to the Reload Index and resume processing
0152  * 0x1ff indicates perpetual loop, infinite reload until the channel is stopped
0153  */
0154 #define CPPI5_INFO0_TRDESC_RLDCNT_SHIFT     (20U)
0155 #define CPPI5_INFO0_TRDESC_RLDCNT_MASK      GENMASK(28, 20)
0156 #define CPPI5_INFO0_TRDESC_RLDCNT_MAX       (0x1ff)
0157 #define CPPI5_INFO0_TRDESC_RLDCNT_INFINITE  CPPI5_INFO0_TRDESC_RLDCNT_MAX
0158 #define CPPI5_INFO0_TRDESC_RLDIDX_SHIFT     (14U)
0159 #define CPPI5_INFO0_TRDESC_RLDIDX_MASK      GENMASK(19, 14)
0160 #define CPPI5_INFO0_TRDESC_RLDIDX_MAX       (0x3f)
0161 #define CPPI5_INFO0_TRDESC_LASTIDX_SHIFT    (0)
0162 #define CPPI5_INFO0_TRDESC_LASTIDX_MASK     GENMASK(13, 0)
0163 
0164 #define CPPI5_INFO1_TRDESC_RECSIZE_SHIFT    (24U)
0165 #define CPPI5_INFO1_TRDESC_RECSIZE_MASK     GENMASK(26, 24)
0166 #define   CPPI5_INFO1_TRDESC_RECSIZE_VAL_16B    (0)
0167 #define   CPPI5_INFO1_TRDESC_RECSIZE_VAL_32B    (1U)
0168 #define   CPPI5_INFO1_TRDESC_RECSIZE_VAL_64B    (2U)
0169 #define   CPPI5_INFO1_TRDESC_RECSIZE_VAL_128B   (3U)
0170 
0171 static inline void cppi5_desc_dump(void *desc, u32 size)
0172 {
0173     print_hex_dump(KERN_ERR, "dump udmap_desc: ", DUMP_PREFIX_NONE,
0174                32, 4, desc, size, false);
0175 }
0176 
0177 #define CPPI5_TDCM_MARKER           (0x1)
0178 /**
0179  * cppi5_desc_is_tdcm - check if the paddr indicates Teardown Complete Message
0180  * @paddr: Physical address of the packet popped from the ring
0181  *
0182  * Returns true if the address indicates TDCM
0183  */
0184 static inline bool cppi5_desc_is_tdcm(dma_addr_t paddr)
0185 {
0186     return (paddr & CPPI5_TDCM_MARKER) ? true : false;
0187 }
0188 
0189 /**
0190  * cppi5_desc_get_type - get descriptor type
0191  * @desc_hdr: packet descriptor/TR header
0192  *
0193  * Returns descriptor type:
0194  * CPPI5_INFO0_DESC_TYPE_VAL_HOST
0195  * CPPI5_INFO0_DESC_TYPE_VAL_MONO
0196  * CPPI5_INFO0_DESC_TYPE_VAL_TR
0197  */
0198 static inline u32 cppi5_desc_get_type(struct cppi5_desc_hdr_t *desc_hdr)
0199 {
0200     return (desc_hdr->pkt_info0 & CPPI5_INFO0_HDESC_TYPE_MASK) >>
0201         CPPI5_INFO0_HDESC_TYPE_SHIFT;
0202 }
0203 
0204 /**
0205  * cppi5_desc_get_errflags - get Error Flags from Desc
0206  * @desc_hdr: packet/TR descriptor header
0207  *
0208  * Returns Error Flags from Packet/TR Descriptor
0209  */
0210 static inline u32 cppi5_desc_get_errflags(struct cppi5_desc_hdr_t *desc_hdr)
0211 {
0212     return (desc_hdr->pkt_info1 & CPPI5_INFO1_DESC_PKTERROR_MASK) >>
0213         CPPI5_INFO1_DESC_PKTERROR_SHIFT;
0214 }
0215 
0216 /**
0217  * cppi5_desc_get_pktids - get Packet and Flow ids from Desc
0218  * @desc_hdr: packet/TR descriptor header
0219  * @pkt_id: Packet ID
0220  * @flow_id: Flow ID
0221  *
0222  * Returns Packet and Flow ids from packet/TR descriptor
0223  */
0224 static inline void cppi5_desc_get_pktids(struct cppi5_desc_hdr_t *desc_hdr,
0225                      u32 *pkt_id, u32 *flow_id)
0226 {
0227     *pkt_id = (desc_hdr->pkt_info1 & CPPI5_INFO1_DESC_PKTID_MASK) >>
0228            CPPI5_INFO1_DESC_PKTID_SHIFT;
0229     *flow_id = (desc_hdr->pkt_info1 & CPPI5_INFO1_DESC_FLOWID_MASK) >>
0230             CPPI5_INFO1_DESC_FLOWID_SHIFT;
0231 }
0232 
0233 /**
0234  * cppi5_desc_set_pktids - set Packet and Flow ids in Desc
0235  * @desc_hdr: packet/TR descriptor header
0236  * @pkt_id: Packet ID
0237  * @flow_id: Flow ID
0238  */
0239 static inline void cppi5_desc_set_pktids(struct cppi5_desc_hdr_t *desc_hdr,
0240                      u32 pkt_id, u32 flow_id)
0241 {
0242     desc_hdr->pkt_info1 &= ~(CPPI5_INFO1_DESC_PKTID_MASK |
0243                  CPPI5_INFO1_DESC_FLOWID_MASK);
0244     desc_hdr->pkt_info1 |= (pkt_id << CPPI5_INFO1_DESC_PKTID_SHIFT) &
0245                 CPPI5_INFO1_DESC_PKTID_MASK;
0246     desc_hdr->pkt_info1 |= (flow_id << CPPI5_INFO1_DESC_FLOWID_SHIFT) &
0247                 CPPI5_INFO1_DESC_FLOWID_MASK;
0248 }
0249 
0250 /**
0251  * cppi5_desc_set_retpolicy - set Packet Return Policy in Desc
0252  * @desc_hdr: packet/TR descriptor header
0253  * @flags: fags, supported values
0254  *  CPPI5_INFO2_HDESC_RETPOLICY
0255  *  CPPI5_INFO2_HDESC_EARLYRET
0256  *  CPPI5_INFO2_DESC_RETPUSHPOLICY
0257  * @return_ring_id: Packet Return Queue/Ring id, value 0xFFFF reserved
0258  */
0259 static inline void cppi5_desc_set_retpolicy(struct cppi5_desc_hdr_t *desc_hdr,
0260                         u32 flags, u32 return_ring_id)
0261 {
0262     desc_hdr->pkt_info2 &= ~(CPPI5_INFO2_DESC_RETP_MASK |
0263                  CPPI5_INFO2_DESC_RETQ_MASK);
0264     desc_hdr->pkt_info2 |= flags & CPPI5_INFO2_DESC_RETP_MASK;
0265     desc_hdr->pkt_info2 |= return_ring_id & CPPI5_INFO2_DESC_RETQ_MASK;
0266 }
0267 
0268 /**
0269  * cppi5_desc_get_tags_ids - get Packet Src/Dst Tags from Desc
0270  * @desc_hdr: packet/TR descriptor header
0271  * @src_tag_id: Source Tag
0272  * @dst_tag_id: Dest Tag
0273  *
0274  * Returns Packet Src/Dst Tags from packet/TR descriptor
0275  */
0276 static inline void cppi5_desc_get_tags_ids(struct cppi5_desc_hdr_t *desc_hdr,
0277                        u32 *src_tag_id, u32 *dst_tag_id)
0278 {
0279     if (src_tag_id)
0280         *src_tag_id = (desc_hdr->src_dst_tag &
0281                   CPPI5_INFO3_DESC_SRCTAG_MASK) >>
0282                   CPPI5_INFO3_DESC_SRCTAG_SHIFT;
0283     if (dst_tag_id)
0284         *dst_tag_id = desc_hdr->src_dst_tag &
0285                   CPPI5_INFO3_DESC_DSTTAG_MASK;
0286 }
0287 
0288 /**
0289  * cppi5_desc_set_tags_ids - set Packet Src/Dst Tags in HDesc
0290  * @desc_hdr: packet/TR descriptor header
0291  * @src_tag_id: Source Tag
0292  * @dst_tag_id: Dest Tag
0293  *
0294  * Returns Packet Src/Dst Tags from packet/TR descriptor
0295  */
0296 static inline void cppi5_desc_set_tags_ids(struct cppi5_desc_hdr_t *desc_hdr,
0297                        u32 src_tag_id, u32 dst_tag_id)
0298 {
0299     desc_hdr->src_dst_tag = (src_tag_id << CPPI5_INFO3_DESC_SRCTAG_SHIFT) &
0300                 CPPI5_INFO3_DESC_SRCTAG_MASK;
0301     desc_hdr->src_dst_tag |= dst_tag_id & CPPI5_INFO3_DESC_DSTTAG_MASK;
0302 }
0303 
0304 /**
0305  * cppi5_hdesc_calc_size - Calculate Host Packet Descriptor size
0306  * @epib: is EPIB present
0307  * @psdata_size: PSDATA size
0308  * @sw_data_size: SWDATA size
0309  *
0310  * Returns required Host Packet Descriptor size
0311  * 0 - if PSDATA > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE
0312  */
0313 static inline u32 cppi5_hdesc_calc_size(bool epib, u32 psdata_size,
0314                     u32 sw_data_size)
0315 {
0316     u32 desc_size;
0317 
0318     if (psdata_size > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE)
0319         return 0;
0320 
0321     desc_size = sizeof(struct cppi5_host_desc_t) + psdata_size +
0322             sw_data_size;
0323 
0324     if (epib)
0325         desc_size += CPPI5_INFO0_HDESC_EPIB_SIZE;
0326 
0327     return ALIGN(desc_size, CPPI5_DESC_MIN_ALIGN);
0328 }
0329 
0330 /**
0331  * cppi5_hdesc_init - Init Host Packet Descriptor size
0332  * @desc: Host packet descriptor
0333  * @flags: supported values
0334  *  CPPI5_INFO0_HDESC_EPIB_PRESENT
0335  *  CPPI5_INFO0_HDESC_PSINFO_LOCATION
0336  * @psdata_size: PSDATA size
0337  *
0338  * Returns required Host Packet Descriptor size
0339  * 0 - if PSDATA > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE
0340  */
0341 static inline void cppi5_hdesc_init(struct cppi5_host_desc_t *desc, u32 flags,
0342                     u32 psdata_size)
0343 {
0344     desc->hdr.pkt_info0 = (CPPI5_INFO0_DESC_TYPE_VAL_HOST <<
0345                    CPPI5_INFO0_HDESC_TYPE_SHIFT) | (flags);
0346     desc->hdr.pkt_info0 |= ((psdata_size >> 2) <<
0347                 CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT) &
0348                 CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK;
0349     desc->next_desc = 0;
0350 }
0351 
0352 /**
0353  * cppi5_hdesc_update_flags - Replace descriptor flags
0354  * @desc: Host packet descriptor
0355  * @flags: supported values
0356  *  CPPI5_INFO0_HDESC_EPIB_PRESENT
0357  *  CPPI5_INFO0_HDESC_PSINFO_LOCATION
0358  */
0359 static inline void cppi5_hdesc_update_flags(struct cppi5_host_desc_t *desc,
0360                         u32 flags)
0361 {
0362     desc->hdr.pkt_info0 &= ~(CPPI5_INFO0_HDESC_EPIB_PRESENT |
0363                  CPPI5_INFO0_HDESC_PSINFO_LOCATION);
0364     desc->hdr.pkt_info0 |= flags;
0365 }
0366 
0367 /**
0368  * cppi5_hdesc_update_psdata_size - Replace PSdata size
0369  * @desc: Host packet descriptor
0370  * @psdata_size: PSDATA size
0371  */
0372 static inline void
0373 cppi5_hdesc_update_psdata_size(struct cppi5_host_desc_t *desc, u32 psdata_size)
0374 {
0375     desc->hdr.pkt_info0 &= ~CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK;
0376     desc->hdr.pkt_info0 |= ((psdata_size >> 2) <<
0377                 CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT) &
0378                 CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK;
0379 }
0380 
0381 /**
0382  * cppi5_hdesc_get_psdata_size - get PSdata size in bytes
0383  * @desc: Host packet descriptor
0384  */
0385 static inline u32 cppi5_hdesc_get_psdata_size(struct cppi5_host_desc_t *desc)
0386 {
0387     u32 psdata_size = 0;
0388 
0389     if (!(desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PSINFO_LOCATION))
0390         psdata_size = (desc->hdr.pkt_info0 &
0391                    CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK) >>
0392                    CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT;
0393 
0394     return (psdata_size << 2);
0395 }
0396 
0397 /**
0398  * cppi5_hdesc_get_pktlen - get Packet Length from HDesc
0399  * @desc: Host packet descriptor
0400  *
0401  * Returns Packet Length from Host Packet Descriptor
0402  */
0403 static inline u32 cppi5_hdesc_get_pktlen(struct cppi5_host_desc_t *desc)
0404 {
0405     return (desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PKTLEN_MASK);
0406 }
0407 
0408 /**
0409  * cppi5_hdesc_set_pktlen - set Packet Length in HDesc
0410  * @desc: Host packet descriptor
0411  */
0412 static inline void cppi5_hdesc_set_pktlen(struct cppi5_host_desc_t *desc,
0413                       u32 pkt_len)
0414 {
0415     desc->hdr.pkt_info0 &= ~CPPI5_INFO0_HDESC_PKTLEN_MASK;
0416     desc->hdr.pkt_info0 |= (pkt_len & CPPI5_INFO0_HDESC_PKTLEN_MASK);
0417 }
0418 
0419 /**
0420  * cppi5_hdesc_get_psflags - get Protocol Specific Flags from HDesc
0421  * @desc: Host packet descriptor
0422  *
0423  * Returns Protocol Specific Flags from Host Packet Descriptor
0424  */
0425 static inline u32 cppi5_hdesc_get_psflags(struct cppi5_host_desc_t *desc)
0426 {
0427     return (desc->hdr.pkt_info1 & CPPI5_INFO1_HDESC_PSFLGS_MASK) >>
0428         CPPI5_INFO1_HDESC_PSFLGS_SHIFT;
0429 }
0430 
0431 /**
0432  * cppi5_hdesc_set_psflags - set Protocol Specific Flags in HDesc
0433  * @desc: Host packet descriptor
0434  */
0435 static inline void cppi5_hdesc_set_psflags(struct cppi5_host_desc_t *desc,
0436                        u32 ps_flags)
0437 {
0438     desc->hdr.pkt_info1 &= ~CPPI5_INFO1_HDESC_PSFLGS_MASK;
0439     desc->hdr.pkt_info1 |= (ps_flags <<
0440                 CPPI5_INFO1_HDESC_PSFLGS_SHIFT) &
0441                 CPPI5_INFO1_HDESC_PSFLGS_MASK;
0442 }
0443 
0444 /**
0445  * cppi5_hdesc_get_errflags - get Packet Type from HDesc
0446  * @desc: Host packet descriptor
0447  */
0448 static inline u32 cppi5_hdesc_get_pkttype(struct cppi5_host_desc_t *desc)
0449 {
0450     return (desc->hdr.pkt_info2 & CPPI5_INFO2_HDESC_PKTTYPE_MASK) >>
0451         CPPI5_INFO2_HDESC_PKTTYPE_SHIFT;
0452 }
0453 
0454 /**
0455  * cppi5_hdesc_get_errflags - set Packet Type in HDesc
0456  * @desc: Host packet descriptor
0457  * @pkt_type: Packet Type
0458  */
0459 static inline void cppi5_hdesc_set_pkttype(struct cppi5_host_desc_t *desc,
0460                        u32 pkt_type)
0461 {
0462     desc->hdr.pkt_info2 &= ~CPPI5_INFO2_HDESC_PKTTYPE_MASK;
0463     desc->hdr.pkt_info2 |=
0464             (pkt_type << CPPI5_INFO2_HDESC_PKTTYPE_SHIFT) &
0465              CPPI5_INFO2_HDESC_PKTTYPE_MASK;
0466 }
0467 
0468 /**
0469  * cppi5_hdesc_attach_buf - attach buffer to HDesc
0470  * @desc: Host packet descriptor
0471  * @buf: Buffer physical address
0472  * @buf_data_len: Buffer length
0473  * @obuf: Original Buffer physical address
0474  * @obuf_len: Original Buffer length
0475  *
0476  * Attaches buffer to Host Packet Descriptor
0477  */
0478 static inline void cppi5_hdesc_attach_buf(struct cppi5_host_desc_t *desc,
0479                       dma_addr_t buf, u32 buf_data_len,
0480                       dma_addr_t obuf, u32 obuf_len)
0481 {
0482     desc->buf_ptr = buf;
0483     desc->buf_info1 = buf_data_len & CPPI5_BUFINFO1_HDESC_DATA_LEN_MASK;
0484     desc->org_buf_ptr = obuf;
0485     desc->org_buf_len = obuf_len & CPPI5_OBUFINFO0_HDESC_BUF_LEN_MASK;
0486 }
0487 
0488 static inline void cppi5_hdesc_get_obuf(struct cppi5_host_desc_t *desc,
0489                     dma_addr_t *obuf, u32 *obuf_len)
0490 {
0491     *obuf = desc->org_buf_ptr;
0492     *obuf_len = desc->org_buf_len & CPPI5_OBUFINFO0_HDESC_BUF_LEN_MASK;
0493 }
0494 
0495 static inline void cppi5_hdesc_reset_to_original(struct cppi5_host_desc_t *desc)
0496 {
0497     desc->buf_ptr = desc->org_buf_ptr;
0498     desc->buf_info1 = desc->org_buf_len;
0499 }
0500 
0501 /**
0502  * cppi5_hdesc_link_hbdesc - link Host Buffer Descriptor to HDesc
0503  * @desc: Host Packet Descriptor
0504  * @buf_desc: Host Buffer Descriptor physical address
0505  *
0506  * add and link Host Buffer Descriptor to HDesc
0507  */
0508 static inline void cppi5_hdesc_link_hbdesc(struct cppi5_host_desc_t *desc,
0509                        dma_addr_t hbuf_desc)
0510 {
0511     desc->next_desc = hbuf_desc;
0512 }
0513 
0514 static inline dma_addr_t
0515 cppi5_hdesc_get_next_hbdesc(struct cppi5_host_desc_t *desc)
0516 {
0517     return (dma_addr_t)desc->next_desc;
0518 }
0519 
0520 static inline void cppi5_hdesc_reset_hbdesc(struct cppi5_host_desc_t *desc)
0521 {
0522     desc->hdr = (struct cppi5_desc_hdr_t) { 0 };
0523     desc->next_desc = 0;
0524 }
0525 
0526 /**
0527  * cppi5_hdesc_epib_present -  check if EPIB present
0528  * @desc_hdr: packet descriptor/TR header
0529  *
0530  * Returns true if EPIB present in the packet
0531  */
0532 static inline bool cppi5_hdesc_epib_present(struct cppi5_desc_hdr_t *desc_hdr)
0533 {
0534     return !!(desc_hdr->pkt_info0 & CPPI5_INFO0_HDESC_EPIB_PRESENT);
0535 }
0536 
0537 /**
0538  * cppi5_hdesc_get_psdata -  Get pointer on PSDATA
0539  * @desc: Host packet descriptor
0540  *
0541  * Returns pointer on PSDATA in HDesc.
0542  * NULL - if ps_data placed at the start of data buffer.
0543  */
0544 static inline void *cppi5_hdesc_get_psdata(struct cppi5_host_desc_t *desc)
0545 {
0546     u32 psdata_size;
0547     void *psdata;
0548 
0549     if (desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PSINFO_LOCATION)
0550         return NULL;
0551 
0552     psdata_size = (desc->hdr.pkt_info0 &
0553                CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK) >>
0554                CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT;
0555 
0556     if (!psdata_size)
0557         return NULL;
0558 
0559     psdata = &desc->epib;
0560 
0561     if (cppi5_hdesc_epib_present(&desc->hdr))
0562         psdata += CPPI5_INFO0_HDESC_EPIB_SIZE;
0563 
0564     return psdata;
0565 }
0566 
0567 /**
0568  * cppi5_hdesc_get_swdata -  Get pointer on swdata
0569  * @desc: Host packet descriptor
0570  *
0571  * Returns pointer on SWDATA in HDesc.
0572  * NOTE. It's caller responsibility to be sure hdesc actually has swdata.
0573  */
0574 static inline void *cppi5_hdesc_get_swdata(struct cppi5_host_desc_t *desc)
0575 {
0576     u32 psdata_size = 0;
0577     void *swdata;
0578 
0579     if (!(desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PSINFO_LOCATION))
0580         psdata_size = (desc->hdr.pkt_info0 &
0581                    CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK) >>
0582                    CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT;
0583 
0584     swdata = &desc->epib;
0585 
0586     if (cppi5_hdesc_epib_present(&desc->hdr))
0587         swdata += CPPI5_INFO0_HDESC_EPIB_SIZE;
0588 
0589     swdata += (psdata_size << 2);
0590 
0591     return swdata;
0592 }
0593 
0594 /* ================================== TR ================================== */
0595 
0596 #define CPPI5_TR_TYPE_SHIFT         (0U)
0597 #define CPPI5_TR_TYPE_MASK          GENMASK(3, 0)
0598 #define CPPI5_TR_STATIC             BIT(4)
0599 #define CPPI5_TR_WAIT               BIT(5)
0600 #define CPPI5_TR_EVENT_SIZE_SHIFT       (6U)
0601 #define CPPI5_TR_EVENT_SIZE_MASK        GENMASK(7, 6)
0602 #define CPPI5_TR_TRIGGER0_SHIFT         (8U)
0603 #define CPPI5_TR_TRIGGER0_MASK          GENMASK(9, 8)
0604 #define CPPI5_TR_TRIGGER0_TYPE_SHIFT        (10U)
0605 #define CPPI5_TR_TRIGGER0_TYPE_MASK     GENMASK(11, 10)
0606 #define CPPI5_TR_TRIGGER1_SHIFT         (12U)
0607 #define CPPI5_TR_TRIGGER1_MASK          GENMASK(13, 12)
0608 #define CPPI5_TR_TRIGGER1_TYPE_SHIFT        (14U)
0609 #define CPPI5_TR_TRIGGER1_TYPE_MASK     GENMASK(15, 14)
0610 #define CPPI5_TR_CMD_ID_SHIFT           (16U)
0611 #define CPPI5_TR_CMD_ID_MASK            GENMASK(23, 16)
0612 #define CPPI5_TR_CSF_FLAGS_SHIFT        (24U)
0613 #define CPPI5_TR_CSF_FLAGS_MASK         GENMASK(31, 24)
0614 #define   CPPI5_TR_CSF_SA_INDIRECT      BIT(0)
0615 #define   CPPI5_TR_CSF_DA_INDIRECT      BIT(1)
0616 #define   CPPI5_TR_CSF_SUPR_EVT         BIT(2)
0617 #define   CPPI5_TR_CSF_EOL_ADV_SHIFT        (4U)
0618 #define   CPPI5_TR_CSF_EOL_ADV_MASK     GENMASK(6, 4)
0619 #define   CPPI5_TR_CSF_EOP          BIT(7)
0620 
0621 /**
0622  * enum cppi5_tr_types - TR types
0623  * @CPPI5_TR_TYPE0: One dimensional data move
0624  * @CPPI5_TR_TYPE1: Two dimensional data move
0625  * @CPPI5_TR_TYPE2: Three dimensional data move
0626  * @CPPI5_TR_TYPE3: Four dimensional data move
0627  * @CPPI5_TR_TYPE4: Four dimensional data move with data formatting
0628  * @CPPI5_TR_TYPE5: Four dimensional Cache Warm
0629  * @CPPI5_TR_TYPE8: Four Dimensional Block Move
0630  * @CPPI5_TR_TYPE9: Four Dimensional Block Move with Repacking
0631  * @CPPI5_TR_TYPE10:    Two Dimensional Block Move
0632  * @CPPI5_TR_TYPE11:    Two Dimensional Block Move with Repacking
0633  * @CPPI5_TR_TYPE15:    Four Dimensional Block Move with Repacking and
0634  *          Indirection
0635  */
0636 enum cppi5_tr_types {
0637     CPPI5_TR_TYPE0 = 0,
0638     CPPI5_TR_TYPE1,
0639     CPPI5_TR_TYPE2,
0640     CPPI5_TR_TYPE3,
0641     CPPI5_TR_TYPE4,
0642     CPPI5_TR_TYPE5,
0643     /* type6-7: Reserved */
0644     CPPI5_TR_TYPE8 = 8,
0645     CPPI5_TR_TYPE9,
0646     CPPI5_TR_TYPE10,
0647     CPPI5_TR_TYPE11,
0648     /* type12-14: Reserved */
0649     CPPI5_TR_TYPE15 = 15,
0650     CPPI5_TR_TYPE_MAX
0651 };
0652 
0653 /**
0654  * enum cppi5_tr_event_size - TR Flags EVENT_SIZE field specifies when an event
0655  *                is generated for each TR.
0656  * @CPPI5_TR_EVENT_SIZE_COMPLETION: When TR is complete and all status for
0657  *                  the TR has been received
0658  * @CPPI5_TR_EVENT_SIZE_ICNT1_DEC:  Type 0: when the last data transaction
0659  *                  is sent for the TR
0660  *                  Type 1-11: when ICNT1 is decremented
0661  * @CPPI5_TR_EVENT_SIZE_ICNT2_DEC:  Type 0-1,10-11: when the last data
0662  *                  transaction is sent for the TR
0663  *                  All other types: when ICNT2 is
0664  *                  decremented
0665  * @CPPI5_TR_EVENT_SIZE_ICNT3_DEC:  Type 0-2,10-11: when the last data
0666  *                  transaction is sent for the TR
0667  *                  All other types: when ICNT3 is
0668  *                  decremented
0669  */
0670 enum cppi5_tr_event_size {
0671     CPPI5_TR_EVENT_SIZE_COMPLETION,
0672     CPPI5_TR_EVENT_SIZE_ICNT1_DEC,
0673     CPPI5_TR_EVENT_SIZE_ICNT2_DEC,
0674     CPPI5_TR_EVENT_SIZE_ICNT3_DEC,
0675     CPPI5_TR_EVENT_SIZE_MAX
0676 };
0677 
0678 /**
0679  * enum cppi5_tr_trigger - TR Flags TRIGGERx field specifies the type of trigger
0680  *             used to enable the TR to transfer data as specified
0681  *             by TRIGGERx_TYPE field.
0682  * @CPPI5_TR_TRIGGER_NONE:      No trigger
0683  * @CPPI5_TR_TRIGGER_GLOBAL0:       Global trigger 0
0684  * @CPPI5_TR_TRIGGER_GLOBAL1:       Global trigger 1
0685  * @CPPI5_TR_TRIGGER_LOCAL_EVENT:   Local Event
0686  */
0687 enum cppi5_tr_trigger {
0688     CPPI5_TR_TRIGGER_NONE,
0689     CPPI5_TR_TRIGGER_GLOBAL0,
0690     CPPI5_TR_TRIGGER_GLOBAL1,
0691     CPPI5_TR_TRIGGER_LOCAL_EVENT,
0692     CPPI5_TR_TRIGGER_MAX
0693 };
0694 
0695 /**
0696  * enum cppi5_tr_trigger_type - TR Flags TRIGGERx_TYPE field specifies the type
0697  *              of data transfer that will be enabled by
0698  *              receiving a trigger as specified by TRIGGERx.
0699  * @CPPI5_TR_TRIGGER_TYPE_ICNT1_DEC:    The second inner most loop (ICNT1) will
0700  *                  be decremented by 1
0701  * @CPPI5_TR_TRIGGER_TYPE_ICNT2_DEC:    The third inner most loop (ICNT2) will
0702  *                  be decremented by 1
0703  * @CPPI5_TR_TRIGGER_TYPE_ICNT3_DEC:    The outer most loop (ICNT3) will be
0704  *                  decremented by 1
0705  * @CPPI5_TR_TRIGGER_TYPE_ALL:      The entire TR will be allowed to
0706  *                  complete
0707  */
0708 enum cppi5_tr_trigger_type {
0709     CPPI5_TR_TRIGGER_TYPE_ICNT1_DEC,
0710     CPPI5_TR_TRIGGER_TYPE_ICNT2_DEC,
0711     CPPI5_TR_TRIGGER_TYPE_ICNT3_DEC,
0712     CPPI5_TR_TRIGGER_TYPE_ALL,
0713     CPPI5_TR_TRIGGER_TYPE_MAX
0714 };
0715 
0716 typedef u32 cppi5_tr_flags_t;
0717 
0718 /**
0719  * struct cppi5_tr_type0_t - Type 0 (One dimensional data move) TR (16 byte)
0720  * @flags:      TR flags (type, triggers, event, configuration)
0721  * @icnt0:      Total loop iteration count for level 0 (innermost)
0722  * @_reserved:      Not used
0723  * @addr:       Starting address for the source data or destination data
0724  */
0725 struct cppi5_tr_type0_t {
0726     cppi5_tr_flags_t flags;
0727     u16 icnt0;
0728     u16 _reserved;
0729     u64 addr;
0730 } __aligned(16) __packed;
0731 
0732 /**
0733  * struct cppi5_tr_type1_t - Type 1 (Two dimensional data move) TR (32 byte)
0734  * @flags:      TR flags (type, triggers, event, configuration)
0735  * @icnt0:      Total loop iteration count for level 0 (innermost)
0736  * @icnt1:      Total loop iteration count for level 1
0737  * @addr:       Starting address for the source data or destination data
0738  * @dim1:       Signed dimension for loop level 1
0739  */
0740 struct cppi5_tr_type1_t {
0741     cppi5_tr_flags_t flags;
0742     u16 icnt0;
0743     u16 icnt1;
0744     u64 addr;
0745     s32 dim1;
0746 } __aligned(32) __packed;
0747 
0748 /**
0749  * struct cppi5_tr_type2_t - Type 2 (Three dimensional data move) TR (32 byte)
0750  * @flags:      TR flags (type, triggers, event, configuration)
0751  * @icnt0:      Total loop iteration count for level 0 (innermost)
0752  * @icnt1:      Total loop iteration count for level 1
0753  * @addr:       Starting address for the source data or destination data
0754  * @dim1:       Signed dimension for loop level 1
0755  * @icnt2:      Total loop iteration count for level 2
0756  * @_reserved:      Not used
0757  * @dim2:       Signed dimension for loop level 2
0758  */
0759 struct cppi5_tr_type2_t {
0760     cppi5_tr_flags_t flags;
0761     u16 icnt0;
0762     u16 icnt1;
0763     u64 addr;
0764     s32 dim1;
0765     u16 icnt2;
0766     u16 _reserved;
0767     s32 dim2;
0768 } __aligned(32) __packed;
0769 
0770 /**
0771  * struct cppi5_tr_type3_t - Type 3 (Four dimensional data move) TR (32 byte)
0772  * @flags:      TR flags (type, triggers, event, configuration)
0773  * @icnt0:      Total loop iteration count for level 0 (innermost)
0774  * @icnt1:      Total loop iteration count for level 1
0775  * @addr:       Starting address for the source data or destination data
0776  * @dim1:       Signed dimension for loop level 1
0777  * @icnt2:      Total loop iteration count for level 2
0778  * @icnt3:      Total loop iteration count for level 3 (outermost)
0779  * @dim2:       Signed dimension for loop level 2
0780  * @dim3:       Signed dimension for loop level 3
0781  */
0782 struct cppi5_tr_type3_t {
0783     cppi5_tr_flags_t flags;
0784     u16 icnt0;
0785     u16 icnt1;
0786     u64 addr;
0787     s32 dim1;
0788     u16 icnt2;
0789     u16 icnt3;
0790     s32 dim2;
0791     s32 dim3;
0792 } __aligned(32) __packed;
0793 
0794 /**
0795  * struct cppi5_tr_type15_t - Type 15 (Four Dimensional Block Copy with
0796  *                Repacking and Indirection Support) TR (64 byte)
0797  * @flags:      TR flags (type, triggers, event, configuration)
0798  * @icnt0:      Total loop iteration count for level 0 (innermost) for
0799  *          source
0800  * @icnt1:      Total loop iteration count for level 1 for source
0801  * @addr:       Starting address for the source data
0802  * @dim1:       Signed dimension for loop level 1 for source
0803  * @icnt2:      Total loop iteration count for level 2 for source
0804  * @icnt3:      Total loop iteration count for level 3 (outermost) for
0805  *          source
0806  * @dim2:       Signed dimension for loop level 2 for source
0807  * @dim3:       Signed dimension for loop level 3 for source
0808  * @_reserved:      Not used
0809  * @ddim1:      Signed dimension for loop level 1 for destination
0810  * @daddr:      Starting address for the destination data
0811  * @ddim2:      Signed dimension for loop level 2 for destination
0812  * @ddim3:      Signed dimension for loop level 3 for destination
0813  * @dicnt0:     Total loop iteration count for level 0 (innermost) for
0814  *          destination
0815  * @dicnt1:     Total loop iteration count for level 1 for destination
0816  * @dicnt2:     Total loop iteration count for level 2 for destination
0817  * @sicnt3:     Total loop iteration count for level 3 (outermost) for
0818  *          destination
0819  */
0820 struct cppi5_tr_type15_t {
0821     cppi5_tr_flags_t flags;
0822     u16 icnt0;
0823     u16 icnt1;
0824     u64 addr;
0825     s32 dim1;
0826     u16 icnt2;
0827     u16 icnt3;
0828     s32 dim2;
0829     s32 dim3;
0830     u32 _reserved;
0831     s32 ddim1;
0832     u64 daddr;
0833     s32 ddim2;
0834     s32 ddim3;
0835     u16 dicnt0;
0836     u16 dicnt1;
0837     u16 dicnt2;
0838     u16 dicnt3;
0839 } __aligned(64) __packed;
0840 
0841 /**
0842  * struct cppi5_tr_resp_t - TR response record
0843  * @status:     Status type and info
0844  * @_reserved:      Not used
0845  * @cmd_id:     Command ID for the TR for TR identification
0846  * @flags:      Configuration Specific Flags
0847  */
0848 struct cppi5_tr_resp_t {
0849     u8 status;
0850     u8 _reserved;
0851     u8 cmd_id;
0852     u8 flags;
0853 } __packed;
0854 
0855 #define CPPI5_TR_RESPONSE_STATUS_TYPE_SHIFT (0U)
0856 #define CPPI5_TR_RESPONSE_STATUS_TYPE_MASK  GENMASK(3, 0)
0857 #define CPPI5_TR_RESPONSE_STATUS_INFO_SHIFT (4U)
0858 #define CPPI5_TR_RESPONSE_STATUS_INFO_MASK  GENMASK(7, 4)
0859 #define CPPI5_TR_RESPONSE_CMDID_SHIFT       (16U)
0860 #define CPPI5_TR_RESPONSE_CMDID_MASK        GENMASK(23, 16)
0861 #define CPPI5_TR_RESPONSE_CFG_SPECIFIC_SHIFT    (24U)
0862 #define CPPI5_TR_RESPONSE_CFG_SPECIFIC_MASK GENMASK(31, 24)
0863 
0864 /**
0865  * enum cppi5_tr_resp_status_type - TR Response Status Type field is used to
0866  *                  determine what type of status is being
0867  *                  returned.
0868  * @CPPI5_TR_RESPONSE_STATUS_NONE:      No error, completion: completed
0869  * @CPPI5_TR_RESPONSE_STATUS_TRANSFER_ERR:  Transfer Error, completion: none
0870  *                      or partially completed
0871  * @CPPI5_TR_RESPONSE_STATUS_ABORTED_ERR:   Aborted Error, completion: none
0872  *                      or partially completed
0873  * @CPPI5_TR_RESPONSE_STATUS_SUBMISSION_ERR:    Submission Error, completion:
0874  *                      none
0875  * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_ERR:   Unsupported Error, completion:
0876  *                      none
0877  * @CPPI5_TR_RESPONSE_STATUS_TRANSFER_EXCEPTION: Transfer Exception, completion:
0878  *                      partially completed
0879  * @CPPI5_TR_RESPONSE_STATUS__TEARDOWN_FLUSH:   Teardown Flush, completion: none
0880  */
0881 enum cppi5_tr_resp_status_type {
0882     CPPI5_TR_RESPONSE_STATUS_NONE,
0883     CPPI5_TR_RESPONSE_STATUS_TRANSFER_ERR,
0884     CPPI5_TR_RESPONSE_STATUS_ABORTED_ERR,
0885     CPPI5_TR_RESPONSE_STATUS_SUBMISSION_ERR,
0886     CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_ERR,
0887     CPPI5_TR_RESPONSE_STATUS_TRANSFER_EXCEPTION,
0888     CPPI5_TR_RESPONSE_STATUS__TEARDOWN_FLUSH,
0889     CPPI5_TR_RESPONSE_STATUS_MAX
0890 };
0891 
0892 /**
0893  * enum cppi5_tr_resp_status_submission - TR Response Status field values which
0894  *                    corresponds Submission Error
0895  * @CPPI5_TR_RESPONSE_STATUS_SUBMISSION_ICNT0:  ICNT0 was 0
0896  * @CPPI5_TR_RESPONSE_STATUS_SUBMISSION_FIFO_FULL: Channel FIFO was full when TR
0897  *                      received
0898  * @CPPI5_TR_RESPONSE_STATUS_SUBMISSION_OWN:    Channel is not owned by the
0899  *                      submitter
0900  */
0901 enum cppi5_tr_resp_status_submission {
0902     CPPI5_TR_RESPONSE_STATUS_SUBMISSION_ICNT0,
0903     CPPI5_TR_RESPONSE_STATUS_SUBMISSION_FIFO_FULL,
0904     CPPI5_TR_RESPONSE_STATUS_SUBMISSION_OWN,
0905     CPPI5_TR_RESPONSE_STATUS_SUBMISSION_MAX
0906 };
0907 
0908 /**
0909  * enum cppi5_tr_resp_status_unsupported - TR Response Status field values which
0910  *                     corresponds Unsupported Error
0911  * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_TR_TYPE:   TR Type not supported
0912  * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_STATIC:    STATIC not supported
0913  * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_EOL:       EOL not supported
0914  * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_CFG_SPECIFIC:  CONFIGURATION SPECIFIC
0915  *                          not supported
0916  * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_AMODE:     AMODE not supported
0917  * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_ELTYPE:    ELTYPE not supported
0918  * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_DFMT:      DFMT not supported
0919  * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_SECTR:     SECTR not supported
0920  * @CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_AMODE_SPECIFIC: AMODE SPECIFIC field
0921  *                          not supported
0922  */
0923 enum cppi5_tr_resp_status_unsupported {
0924     CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_TR_TYPE,
0925     CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_STATIC,
0926     CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_EOL,
0927     CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_CFG_SPECIFIC,
0928     CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_AMODE,
0929     CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_ELTYPE,
0930     CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_DFMT,
0931     CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_SECTR,
0932     CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_AMODE_SPECIFIC,
0933     CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_MAX
0934 };
0935 
0936 /**
0937  * cppi5_trdesc_calc_size - Calculate TR Descriptor size
0938  * @tr_count: number of TR records
0939  * @tr_size: Nominal size of TR record (max) [16, 32, 64, 128]
0940  *
0941  * Returns required TR Descriptor size
0942  */
0943 static inline size_t cppi5_trdesc_calc_size(u32 tr_count, u32 tr_size)
0944 {
0945     /*
0946      * The Size of a TR descriptor is:
0947      * 1 x tr_size : the first 16 bytes is used by the packet info block +
0948      * tr_count x tr_size : Transfer Request Records +
0949      * tr_count x sizeof(struct cppi5_tr_resp_t) : Transfer Response Records
0950      */
0951     return tr_size * (tr_count + 1) +
0952         sizeof(struct cppi5_tr_resp_t) * tr_count;
0953 }
0954 
0955 /**
0956  * cppi5_trdesc_init - Init TR Descriptor
0957  * @desc: TR Descriptor
0958  * @tr_count: number of TR records
0959  * @tr_size: Nominal size of TR record (max) [16, 32, 64, 128]
0960  * @reload_idx: Absolute index to jump to on the 2nd and following passes
0961  *      through the TR packet.
0962  * @reload_count: Number of times to jump from last entry to reload_idx. 0x1ff
0963  *        indicates infinite looping.
0964  *
0965  * Init TR Descriptor
0966  */
0967 static inline void cppi5_trdesc_init(struct cppi5_desc_hdr_t *desc_hdr,
0968                      u32 tr_count, u32 tr_size, u32 reload_idx,
0969                      u32 reload_count)
0970 {
0971     desc_hdr->pkt_info0 = CPPI5_INFO0_DESC_TYPE_VAL_TR <<
0972                   CPPI5_INFO0_HDESC_TYPE_SHIFT;
0973     desc_hdr->pkt_info0 |=
0974             (reload_count << CPPI5_INFO0_TRDESC_RLDCNT_SHIFT) &
0975             CPPI5_INFO0_TRDESC_RLDCNT_MASK;
0976     desc_hdr->pkt_info0 |=
0977             (reload_idx << CPPI5_INFO0_TRDESC_RLDIDX_SHIFT) &
0978             CPPI5_INFO0_TRDESC_RLDIDX_MASK;
0979     desc_hdr->pkt_info0 |= (tr_count - 1) & CPPI5_INFO0_TRDESC_LASTIDX_MASK;
0980 
0981     desc_hdr->pkt_info1 |= ((ffs(tr_size >> 4) - 1) <<
0982                 CPPI5_INFO1_TRDESC_RECSIZE_SHIFT) &
0983                 CPPI5_INFO1_TRDESC_RECSIZE_MASK;
0984 }
0985 
0986 /**
0987  * cppi5_tr_init - Init TR record
0988  * @flags: Pointer to the TR's flags
0989  * @type: TR type
0990  * @static_tr: TR is static
0991  * @wait: Wait for TR completion before allow the next TR to start
0992  * @event_size: output event generation cfg
0993  * @cmd_id: TR identifier (application specifics)
0994  *
0995  * Init TR record
0996  */
0997 static inline void cppi5_tr_init(cppi5_tr_flags_t *flags,
0998                  enum cppi5_tr_types type, bool static_tr,
0999                  bool wait, enum cppi5_tr_event_size event_size,
1000                  u32 cmd_id)
1001 {
1002     *flags = type;
1003     *flags |= (event_size << CPPI5_TR_EVENT_SIZE_SHIFT) &
1004           CPPI5_TR_EVENT_SIZE_MASK;
1005 
1006     *flags |= (cmd_id << CPPI5_TR_CMD_ID_SHIFT) &
1007           CPPI5_TR_CMD_ID_MASK;
1008 
1009     if (static_tr && (type == CPPI5_TR_TYPE8 || type == CPPI5_TR_TYPE9))
1010         *flags |= CPPI5_TR_STATIC;
1011 
1012     if (wait)
1013         *flags |= CPPI5_TR_WAIT;
1014 }
1015 
1016 /**
1017  * cppi5_tr_set_trigger - Configure trigger0/1 and trigger0/1_type
1018  * @flags: Pointer to the TR's flags
1019  * @trigger0: trigger0 selection
1020  * @trigger0_type: type of data transfer that will be enabled by trigger0
1021  * @trigger1: trigger1 selection
1022  * @trigger1_type: type of data transfer that will be enabled by trigger1
1023  *
1024  * Configure the triggers for the TR
1025  */
1026 static inline void cppi5_tr_set_trigger(cppi5_tr_flags_t *flags,
1027         enum cppi5_tr_trigger trigger0,
1028         enum cppi5_tr_trigger_type trigger0_type,
1029         enum cppi5_tr_trigger trigger1,
1030         enum cppi5_tr_trigger_type trigger1_type)
1031 {
1032     *flags &= ~(CPPI5_TR_TRIGGER0_MASK | CPPI5_TR_TRIGGER0_TYPE_MASK |
1033             CPPI5_TR_TRIGGER1_MASK | CPPI5_TR_TRIGGER1_TYPE_MASK);
1034     *flags |= (trigger0 << CPPI5_TR_TRIGGER0_SHIFT) &
1035           CPPI5_TR_TRIGGER0_MASK;
1036     *flags |= (trigger0_type << CPPI5_TR_TRIGGER0_TYPE_SHIFT) &
1037           CPPI5_TR_TRIGGER0_TYPE_MASK;
1038 
1039     *flags |= (trigger1 << CPPI5_TR_TRIGGER1_SHIFT) &
1040           CPPI5_TR_TRIGGER1_MASK;
1041     *flags |= (trigger1_type << CPPI5_TR_TRIGGER1_TYPE_SHIFT) &
1042           CPPI5_TR_TRIGGER1_TYPE_MASK;
1043 }
1044 
1045 /**
1046  * cppi5_tr_cflag_set - Update the Configuration specific flags
1047  * @flags: Pointer to the TR's flags
1048  * @csf: Configuration specific flags
1049  *
1050  * Set a bit in Configuration Specific Flags section of the TR flags.
1051  */
1052 static inline void cppi5_tr_csf_set(cppi5_tr_flags_t *flags, u32 csf)
1053 {
1054     *flags &= ~CPPI5_TR_CSF_FLAGS_MASK;
1055     *flags |= (csf << CPPI5_TR_CSF_FLAGS_SHIFT) &
1056           CPPI5_TR_CSF_FLAGS_MASK;
1057 }
1058 
1059 #endif /* __TI_CPPI5_H__ */
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