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0001 /* SPDX-License-Identifier: GPL-2.0 */ 0002 0003 #ifndef _SPRD_DMA_H_ 0004 #define _SPRD_DMA_H_ 0005 0006 #define SPRD_DMA_REQ_SHIFT 8 0007 #define SPRD_DMA_TRG_MODE_SHIFT 16 0008 #define SPRD_DMA_CHN_MODE_SHIFT 24 0009 #define SPRD_DMA_FLAGS(chn_mode, trg_mode, req_mode, int_type) \ 0010 ((chn_mode) << SPRD_DMA_CHN_MODE_SHIFT | \ 0011 (trg_mode) << SPRD_DMA_TRG_MODE_SHIFT | \ 0012 (req_mode) << SPRD_DMA_REQ_SHIFT | (int_type)) 0013 0014 /* 0015 * The Spreadtrum DMA controller supports channel 2-stage tansfer, that means 0016 * we can request 2 dma channels, one for source channel, and another one for 0017 * destination channel. Each channel is independent, and has its own 0018 * configurations. Once the source channel's transaction is done, it will 0019 * trigger the destination channel's transaction automatically by hardware 0020 * signal. 0021 * 0022 * To support 2-stage tansfer, we must configure the channel mode and trigger 0023 * mode as below definition. 0024 */ 0025 0026 /* 0027 * enum sprd_dma_chn_mode: define the DMA channel mode for 2-stage transfer 0028 * @SPRD_DMA_CHN_MODE_NONE: No channel mode setting which means channel doesn't 0029 * support the 2-stage transfer. 0030 * @SPRD_DMA_SRC_CHN0: Channel used as source channel 0. 0031 * @SPRD_DMA_SRC_CHN1: Channel used as source channel 1. 0032 * @SPRD_DMA_DST_CHN0: Channel used as destination channel 0. 0033 * @SPRD_DMA_DST_CHN1: Channel used as destination channel 1. 0034 * 0035 * Now the DMA controller can supports 2 groups 2-stage transfer. 0036 */ 0037 enum sprd_dma_chn_mode { 0038 SPRD_DMA_CHN_MODE_NONE, 0039 SPRD_DMA_SRC_CHN0, 0040 SPRD_DMA_SRC_CHN1, 0041 SPRD_DMA_DST_CHN0, 0042 SPRD_DMA_DST_CHN1, 0043 }; 0044 0045 /* 0046 * enum sprd_dma_trg_mode: define the DMA channel trigger mode for 2-stage 0047 * transfer 0048 * @SPRD_DMA_NO_TRG: No trigger setting. 0049 * @SPRD_DMA_FRAG_DONE_TRG: Trigger the transaction of destination channel 0050 * automatically once the source channel's fragment request is done. 0051 * @SPRD_DMA_BLOCK_DONE_TRG: Trigger the transaction of destination channel 0052 * automatically once the source channel's block request is done. 0053 * @SPRD_DMA_TRANS_DONE_TRG: Trigger the transaction of destination channel 0054 * automatically once the source channel's transfer request is done. 0055 * @SPRD_DMA_LIST_DONE_TRG: Trigger the transaction of destination channel 0056 * automatically once the source channel's link-list request is done. 0057 */ 0058 enum sprd_dma_trg_mode { 0059 SPRD_DMA_NO_TRG, 0060 SPRD_DMA_FRAG_DONE_TRG, 0061 SPRD_DMA_BLOCK_DONE_TRG, 0062 SPRD_DMA_TRANS_DONE_TRG, 0063 SPRD_DMA_LIST_DONE_TRG, 0064 }; 0065 0066 /* 0067 * enum sprd_dma_req_mode: define the DMA request mode 0068 * @SPRD_DMA_FRAG_REQ: fragment request mode 0069 * @SPRD_DMA_BLK_REQ: block request mode 0070 * @SPRD_DMA_TRANS_REQ: transaction request mode 0071 * @SPRD_DMA_LIST_REQ: link-list request mode 0072 * 0073 * We have 4 types request mode: fragment mode, block mode, transaction mode 0074 * and linklist mode. One transaction can contain several blocks, one block can 0075 * contain several fragments. Link-list mode means we can save several DMA 0076 * configuration into one reserved memory, then DMA can fetch each DMA 0077 * configuration automatically to start transfer. 0078 */ 0079 enum sprd_dma_req_mode { 0080 SPRD_DMA_FRAG_REQ, 0081 SPRD_DMA_BLK_REQ, 0082 SPRD_DMA_TRANS_REQ, 0083 SPRD_DMA_LIST_REQ, 0084 }; 0085 0086 /* 0087 * enum sprd_dma_int_type: define the DMA interrupt type 0088 * @SPRD_DMA_NO_INT: do not need generate DMA interrupts. 0089 * @SPRD_DMA_FRAG_INT: fragment done interrupt when one fragment request 0090 * is done. 0091 * @SPRD_DMA_BLK_INT: block done interrupt when one block request is done. 0092 * @SPRD_DMA_BLK_FRAG_INT: block and fragment interrupt when one fragment 0093 * or one block request is done. 0094 * @SPRD_DMA_TRANS_INT: tansaction done interrupt when one transaction 0095 * request is done. 0096 * @SPRD_DMA_TRANS_FRAG_INT: transaction and fragment interrupt when one 0097 * transaction request or fragment request is done. 0098 * @SPRD_DMA_TRANS_BLK_INT: transaction and block interrupt when one 0099 * transaction request or block request is done. 0100 * @SPRD_DMA_LIST_INT: link-list done interrupt when one link-list request 0101 * is done. 0102 * @SPRD_DMA_CFGERR_INT: configure error interrupt when configuration is 0103 * incorrect. 0104 */ 0105 enum sprd_dma_int_type { 0106 SPRD_DMA_NO_INT, 0107 SPRD_DMA_FRAG_INT, 0108 SPRD_DMA_BLK_INT, 0109 SPRD_DMA_BLK_FRAG_INT, 0110 SPRD_DMA_TRANS_INT, 0111 SPRD_DMA_TRANS_FRAG_INT, 0112 SPRD_DMA_TRANS_BLK_INT, 0113 SPRD_DMA_LIST_INT, 0114 SPRD_DMA_CFGERR_INT, 0115 }; 0116 0117 /* 0118 * struct sprd_dma_linklist - DMA link-list address structure 0119 * @virt_addr: link-list virtual address to configure link-list node 0120 * @phy_addr: link-list physical address to link DMA transfer 0121 * @wrap_addr: the wrap address for link-list mode, which means once the 0122 * transfer address reaches the wrap address, the next transfer address 0123 * will jump to the address specified by wrap_to register. 0124 * 0125 * The Spreadtrum DMA controller supports the link-list mode, that means slaves 0126 * can supply several groups configurations (each configuration represents one 0127 * DMA transfer) saved in memory, and DMA controller will link these groups 0128 * configurations by writing the physical address of each configuration into the 0129 * link-list register. 0130 * 0131 * Just as shown below, the link-list pointer register will be pointed to the 0132 * physical address of 'configuration 1', and the 'configuration 1' link-list 0133 * pointer will be pointed to 'configuration 2', and so on. 0134 * Once trigger the DMA transfer, the DMA controller will load 'configuration 0135 * 1' to its registers automatically, after 'configuration 1' transaction is 0136 * done, DMA controller will load 'configuration 2' automatically, until all 0137 * DMA transactions are done. 0138 * 0139 * Note: The last link-list pointer should point to the physical address 0140 * of 'configuration 1', which can avoid DMA controller loads incorrect 0141 * configuration when the last configuration transaction is done. 0142 * 0143 * DMA controller linklist memory 0144 * ====================== ----------------------- 0145 *| | | configuration 1 |<--- 0146 *| DMA controller | ------->| | | 0147 *| | | | | | 0148 *| | | | | | 0149 *| | | | | | 0150 *| linklist pointer reg |---- ----| linklist pointer | | 0151 * ====================== | ----------------------- | 0152 * | | 0153 * | ----------------------- | 0154 * | | configuration 2 | | 0155 * --->| | | 0156 * | | | 0157 * | | | 0158 * | | | 0159 * ----| linklist pointer | | 0160 * | ----------------------- | 0161 * | | 0162 * | ----------------------- | 0163 * | | configuration 3 | | 0164 * --->| | | 0165 * | | | 0166 * | . | | 0167 * . | 0168 * . | 0169 * . | 0170 * | . | 0171 * | ----------------------- | 0172 * | | configuration n | | 0173 * --->| | | 0174 * | | | 0175 * | | | 0176 * | | | 0177 * | linklist pointer |---- 0178 * ----------------------- 0179 * 0180 * To support the link-list mode, DMA slaves should allocate one segment memory 0181 * from always-on IRAM or dma coherent memory to store these groups of DMA 0182 * configuration, and pass the virtual and physical address to DMA controller. 0183 */ 0184 struct sprd_dma_linklist { 0185 unsigned long virt_addr; 0186 phys_addr_t phy_addr; 0187 phys_addr_t wrap_addr; 0188 }; 0189 0190 #endif
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