0001
0002 #ifndef _MXS_DMA_H_
0003 #define _MXS_DMA_H_
0004
0005 #include <linux/dmaengine.h>
0006
0007 #define MXS_DMA_CTRL_WAIT4END BIT(31)
0008 #define MXS_DMA_CTRL_WAIT4RDY BIT(30)
0009
0010
0011
0012
0013
0014
0015
0016 static inline struct dma_async_tx_descriptor *mxs_dmaengine_prep_pio(
0017 struct dma_chan *chan, u32 *pio, unsigned int npio,
0018 enum dma_transfer_direction dir, unsigned long flags)
0019 {
0020 return dmaengine_prep_slave_sg(chan, (struct scatterlist *)pio, npio,
0021 dir, flags);
0022 }
0023
0024 #endif