linux/dma/k3-udma-glue.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  *  Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
0004  */
0005
0006 #ifndef K3_UDMA_GLUE_H_
0007 #define K3_UDMA_GLUE_H_
0008
0009 #include <linux/types.h>
0010 #include <linux/soc/ti/k3-ringacc.h>
0011 #include <linux/dma/ti-cppi5.h>
0012
0013 struct k3_udma_glue_tx_channel_cfg {
0014     struct k3_ring_cfg tx_cfg;
0015     struct k3_ring_cfg txcq_cfg;
0016
0017     bool tx_pause_on_err;
0018     bool tx_filt_einfo;
0019     bool tx_filt_pswords;
0020     bool tx_supr_tdpkt;
0021     u32  swdata_size;
0022 };
0023
0024 struct k3_udma_glue_tx_channel;
0025
0026 struct k3_udma_glue_tx_channel *k3_udma_glue_request_tx_chn(struct device *dev,
0027         const char *name, struct k3_udma_glue_tx_channel_cfg *cfg);
0028
0029 void k3_udma_glue_release_tx_chn(struct k3_udma_glue_tx_channel *tx_chn);
0030 int k3_udma_glue_push_tx_chn(struct k3_udma_glue_tx_channel *tx_chn,
0031                  struct cppi5_host_desc_t *desc_tx,
0032                  dma_addr_t desc_dma);
0033 int k3_udma_glue_pop_tx_chn(struct k3_udma_glue_tx_channel *tx_chn,
0034                 dma_addr_t *desc_dma);
0035 int k3_udma_glue_enable_tx_chn(struct k3_udma_glue_tx_channel *tx_chn);
0036 void k3_udma_glue_disable_tx_chn(struct k3_udma_glue_tx_channel *tx_chn);
0037 void k3_udma_glue_tdown_tx_chn(struct k3_udma_glue_tx_channel *tx_chn,
0038                    bool sync);
0039 void k3_udma_glue_reset_tx_chn(struct k3_udma_glue_tx_channel *tx_chn,
0040         void *data, void (*cleanup)(void *data, dma_addr_t desc_dma));
0041 u32 k3_udma_glue_tx_get_hdesc_size(struct k3_udma_glue_tx_channel *tx_chn);
0042 u32 k3_udma_glue_tx_get_txcq_id(struct k3_udma_glue_tx_channel *tx_chn);
0043 int k3_udma_glue_tx_get_irq(struct k3_udma_glue_tx_channel *tx_chn);
0044 struct device *
0045     k3_udma_glue_tx_get_dma_device(struct k3_udma_glue_tx_channel *tx_chn);
0046 void k3_udma_glue_tx_dma_to_cppi5_addr(struct k3_udma_glue_tx_channel *tx_chn,
0047                        dma_addr_t *addr);
0048 void k3_udma_glue_tx_cppi5_to_dma_addr(struct k3_udma_glue_tx_channel *tx_chn,
0049                        dma_addr_t *addr);
0050
0051 enum {
0052     K3_UDMA_GLUE_SRC_TAG_LO_KEEP = 0,
0053     K3_UDMA_GLUE_SRC_TAG_LO_USE_FLOW_REG = 1,
0054     K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_FLOW_ID = 2,
0055     K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG = 4,
0056 };
0057
0058 /**
0059  * k3_udma_glue_rx_flow_cfg - UDMA RX flow cfg
0060  *
0061  * @rx_cfg:     RX ring configuration
0062  * @rxfdq_cfg:      RX free Host PD ring configuration
0063  * @ring_rxq_id:    RX ring id (or -1 for any)
0064  * @ring_rxfdq0_id: RX free Host PD ring (FDQ) if (or -1 for any)
0065  * @rx_error_handling:  Rx Error Handling Mode (0 - drop, 1 - re-try)
0066  * @src_tag_lo_sel: Rx Source Tag Low Byte Selector in Host PD
0067  */
0068 struct k3_udma_glue_rx_flow_cfg {
0069     struct k3_ring_cfg rx_cfg;
0070     struct k3_ring_cfg rxfdq_cfg;
0071     int ring_rxq_id;
0072     int ring_rxfdq0_id;
0073     bool rx_error_handling;
0074     int src_tag_lo_sel;
0075 };
0076
0077 /**
0078  * k3_udma_glue_rx_channel_cfg - UDMA RX channel cfg
0079  *
0080  * @psdata_size:    SW Data is present in Host PD of @swdata_size bytes
0081  * @flow_id_base:   first flow_id used by channel.
0082  *          if @flow_id_base = -1 - range of GP rflows will be
0083  *          allocated dynamically.
0084  * @flow_id_num:    number of RX flows used by channel
0085  * @flow_id_use_rxchan_id:  use RX channel id as flow id,
0086  *              used only if @flow_id_num = 1
0087  * @remote      indication that RX channel is remote - some remote CPU
0088  *          core owns and control the RX channel. Linux Host only
0089  *          allowed to attach and configure RX Flow within RX
0090  *          channel. if set - not RX channel operation will be
0091  *          performed by K3 NAVSS DMA glue interface.
0092  * @def_flow_cfg    default RX flow configuration,
0093  *          used only if @flow_id_num = 1
0094  */
0095 struct k3_udma_glue_rx_channel_cfg {
0096     u32  swdata_size;
0097     int  flow_id_base;
0098     int  flow_id_num;
0099     bool flow_id_use_rxchan_id;
0100     bool remote;
0101
0102     struct k3_udma_glue_rx_flow_cfg *def_flow_cfg;
0103 };
0104
0105 struct k3_udma_glue_rx_channel;
0106
0107 struct k3_udma_glue_rx_channel *k3_udma_glue_request_rx_chn(
0108         struct device *dev,
0109         const char *name,
0110         struct k3_udma_glue_rx_channel_cfg *cfg);
0111
0112 void k3_udma_glue_release_rx_chn(struct k3_udma_glue_rx_channel *rx_chn);
0113 int k3_udma_glue_enable_rx_chn(struct k3_udma_glue_rx_channel *rx_chn);
0114 void k3_udma_glue_disable_rx_chn(struct k3_udma_glue_rx_channel *rx_chn);
0115 void k3_udma_glue_tdown_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
0116                    bool sync);
0117 int k3_udma_glue_push_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
0118         u32 flow_num, struct cppi5_host_desc_t *desc_tx,
0119         dma_addr_t desc_dma);
0120 int k3_udma_glue_pop_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
0121         u32 flow_num, dma_addr_t *desc_dma);
0122 int k3_udma_glue_rx_flow_init(struct k3_udma_glue_rx_channel *rx_chn,
0123         u32 flow_idx, struct k3_udma_glue_rx_flow_cfg *flow_cfg);
0124 u32 k3_udma_glue_rx_flow_get_fdq_id(struct k3_udma_glue_rx_channel *rx_chn,
0125                     u32 flow_idx);
0126 u32 k3_udma_glue_rx_get_flow_id_base(struct k3_udma_glue_rx_channel *rx_chn);
0127 int k3_udma_glue_rx_get_irq(struct k3_udma_glue_rx_channel *rx_chn,
0128                 u32 flow_num);
0129 void k3_udma_glue_rx_put_irq(struct k3_udma_glue_rx_channel *rx_chn,
0130                  u32 flow_num);
0131 void k3_udma_glue_reset_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
0132         u32 flow_num, void *data,
0133         void (*cleanup)(void *data, dma_addr_t desc_dma),
0134         bool skip_fdq);
0135 int k3_udma_glue_rx_flow_enable(struct k3_udma_glue_rx_channel *rx_chn,
0136                 u32 flow_idx);
0137 int k3_udma_glue_rx_flow_disable(struct k3_udma_glue_rx_channel *rx_chn,
0138                  u32 flow_idx);
0139 struct device *
0140     k3_udma_glue_rx_get_dma_device(struct k3_udma_glue_rx_channel *rx_chn);
0141 void k3_udma_glue_rx_dma_to_cppi5_addr(struct k3_udma_glue_rx_channel *rx_chn,
0142                        dma_addr_t *addr);
0143 void k3_udma_glue_rx_cppi5_to_dma_addr(struct k3_udma_glue_rx_channel *rx_chn,
0144                        dma_addr_t *addr);
0145
0146 #endif /* K3_UDMA_GLUE_H_ */