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0001 /* SPDX-License-Identifier: GPL-2.0 */ 0002 /* 0003 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com 0004 */ 0005 0006 #ifndef K3_PSIL_H_ 0007 #define K3_PSIL_H_ 0008 0009 #include <linux/types.h> 0010 0011 #define K3_PSIL_DST_THREAD_ID_OFFSET 0x8000 0012 0013 struct device; 0014 0015 /** 0016 * enum udma_tp_level - Channel Throughput Levels 0017 * @UDMA_TP_NORMAL: Normal channel 0018 * @UDMA_TP_HIGH: High Throughput channel 0019 * @UDMA_TP_ULTRAHIGH: Ultra High Throughput channel 0020 */ 0021 enum udma_tp_level { 0022 UDMA_TP_NORMAL = 0, 0023 UDMA_TP_HIGH, 0024 UDMA_TP_ULTRAHIGH, 0025 UDMA_TP_LAST, 0026 }; 0027 0028 /** 0029 * enum psil_endpoint_type - PSI-L Endpoint type 0030 * @PSIL_EP_NATIVE: Normal channel 0031 * @PSIL_EP_PDMA_XY: XY mode PDMA 0032 * @PSIL_EP_PDMA_MCAN: MCAN mode PDMA 0033 * @PSIL_EP_PDMA_AASRC: AASRC mode PDMA 0034 */ 0035 enum psil_endpoint_type { 0036 PSIL_EP_NATIVE = 0, 0037 PSIL_EP_PDMA_XY, 0038 PSIL_EP_PDMA_MCAN, 0039 PSIL_EP_PDMA_AASRC, 0040 }; 0041 0042 /** 0043 * struct psil_endpoint_config - PSI-L Endpoint configuration 0044 * @ep_type: PSI-L endpoint type 0045 * @channel_tpl: Desired throughput level for the channel 0046 * @pkt_mode: If set, the channel must be in Packet mode, otherwise in 0047 * TR mode 0048 * @notdpkt: TDCM must be suppressed on the TX channel 0049 * @needs_epib: Endpoint needs EPIB 0050 * @pdma_acc32: ACC32 must be enabled on the PDMA side 0051 * @pdma_burst: BURST must be enabled on the PDMA side 0052 * @psd_size: If set, PSdata is used by the endpoint 0053 * @mapped_channel_id: PKTDMA thread to channel mapping for mapped channels. 0054 * The thread must be serviced by the specified channel if 0055 * mapped_channel_id is >= 0 in case of PKTDMA 0056 * @flow_start: PKDMA flow range start of mapped channel. Unmapped 0057 * channels use flow_id == chan_id 0058 * @flow_num: PKDMA flow count of mapped channel. Unmapped channels 0059 * use flow_id == chan_id 0060 * @default_flow_id: PKDMA default (r)flow index of mapped channel. 0061 * Must be within the flow range of the mapped channel. 0062 */ 0063 struct psil_endpoint_config { 0064 enum psil_endpoint_type ep_type; 0065 enum udma_tp_level channel_tpl; 0066 0067 unsigned pkt_mode:1; 0068 unsigned notdpkt:1; 0069 unsigned needs_epib:1; 0070 /* PDMA properties, valid for PSIL_EP_PDMA_* */ 0071 unsigned pdma_acc32:1; 0072 unsigned pdma_burst:1; 0073 0074 u32 psd_size; 0075 /* PKDMA mapped channel */ 0076 s16 mapped_channel_id; 0077 /* PKTDMA tflow and rflow ranges for mapped channel */ 0078 u16 flow_start; 0079 u16 flow_num; 0080 s16 default_flow_id; 0081 }; 0082 0083 int psil_set_new_ep_config(struct device *dev, const char *name, 0084 struct psil_endpoint_config *ep_config); 0085 0086 #endif /* K3_PSIL_H_ */
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