linux/dma/ipu-dma.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2008
0004  * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
0005  *
0006  * Copyright (C) 2005-2007 Freescale Semiconductor, Inc.
0007  */
0008
0009 #ifndef __LINUX_DMA_IPU_DMA_H
0010 #define __LINUX_DMA_IPU_DMA_H
0011
0012 #include <linux/types.h>
0013 #include <linux/dmaengine.h>
0014
0015 /* IPU DMA Controller channel definitions. */
0016 enum ipu_channel {
0017     IDMAC_IC_0 = 0,     /* IC (encoding task) to memory */
0018     IDMAC_IC_1 = 1,     /* IC (viewfinder task) to memory */
0019     IDMAC_ADC_0 = 1,
0020     IDMAC_IC_2 = 2,
0021     IDMAC_ADC_1 = 2,
0022     IDMAC_IC_3 = 3,
0023     IDMAC_IC_4 = 4,
0024     IDMAC_IC_5 = 5,
0025     IDMAC_IC_6 = 6,
0026     IDMAC_IC_7 = 7,     /* IC (sensor data) to memory */
0027     IDMAC_IC_8 = 8,
0028     IDMAC_IC_9 = 9,
0029     IDMAC_IC_10 = 10,
0030     IDMAC_IC_11 = 11,
0031     IDMAC_IC_12 = 12,
0032     IDMAC_IC_13 = 13,
0033     IDMAC_SDC_0 = 14,   /* Background synchronous display data */
0034     IDMAC_SDC_1 = 15,   /* Foreground data (overlay) */
0035     IDMAC_SDC_2 = 16,
0036     IDMAC_SDC_3 = 17,
0037     IDMAC_ADC_2 = 18,
0038     IDMAC_ADC_3 = 19,
0039     IDMAC_ADC_4 = 20,
0040     IDMAC_ADC_5 = 21,
0041     IDMAC_ADC_6 = 22,
0042     IDMAC_ADC_7 = 23,
0043     IDMAC_PF_0 = 24,
0044     IDMAC_PF_1 = 25,
0045     IDMAC_PF_2 = 26,
0046     IDMAC_PF_3 = 27,
0047     IDMAC_PF_4 = 28,
0048     IDMAC_PF_5 = 29,
0049     IDMAC_PF_6 = 30,
0050     IDMAC_PF_7 = 31,
0051 };
0052
0053 /* Order significant! */
0054 enum ipu_channel_status {
0055     IPU_CHANNEL_FREE,
0056     IPU_CHANNEL_INITIALIZED,
0057     IPU_CHANNEL_READY,
0058     IPU_CHANNEL_ENABLED,
0059 };
0060
0061 #define IPU_CHANNELS_NUM 32
0062
0063 enum pixel_fmt {
0064     /* 1 byte */
0065     IPU_PIX_FMT_GENERIC,
0066     IPU_PIX_FMT_RGB332,
0067     IPU_PIX_FMT_YUV420P,
0068     IPU_PIX_FMT_YUV422P,
0069     IPU_PIX_FMT_YUV420P2,
0070     IPU_PIX_FMT_YVU422P,
0071     /* 2 bytes */
0072     IPU_PIX_FMT_RGB565,
0073     IPU_PIX_FMT_RGB666,
0074     IPU_PIX_FMT_BGR666,
0075     IPU_PIX_FMT_YUYV,
0076     IPU_PIX_FMT_UYVY,
0077     /* 3 bytes */
0078     IPU_PIX_FMT_RGB24,
0079     IPU_PIX_FMT_BGR24,
0080     /* 4 bytes */
0081     IPU_PIX_FMT_GENERIC_32,
0082     IPU_PIX_FMT_RGB32,
0083     IPU_PIX_FMT_BGR32,
0084     IPU_PIX_FMT_ABGR32,
0085     IPU_PIX_FMT_BGRA32,
0086     IPU_PIX_FMT_RGBA32,
0087 };
0088
0089 enum ipu_color_space {
0090     IPU_COLORSPACE_RGB,
0091     IPU_COLORSPACE_YCBCR,
0092     IPU_COLORSPACE_YUV
0093 };
0094
0095 /*
0096  * Enumeration of IPU rotation modes
0097  */
0098 enum ipu_rotate_mode {
0099     /* Note the enum values correspond to BAM value */
0100     IPU_ROTATE_NONE = 0,
0101     IPU_ROTATE_VERT_FLIP = 1,
0102     IPU_ROTATE_HORIZ_FLIP = 2,
0103     IPU_ROTATE_180 = 3,
0104     IPU_ROTATE_90_RIGHT = 4,
0105     IPU_ROTATE_90_RIGHT_VFLIP = 5,
0106     IPU_ROTATE_90_RIGHT_HFLIP = 6,
0107     IPU_ROTATE_90_LEFT = 7,
0108 };
0109
0110 /*
0111  * Enumeration of DI ports for ADC.
0112  */
0113 enum display_port {
0114     DISP0,
0115     DISP1,
0116     DISP2,
0117     DISP3
0118 };
0119
0120 struct idmac_video_param {
0121     unsigned short      in_width;
0122     unsigned short      in_height;
0123     uint32_t        in_pixel_fmt;
0124     unsigned short      out_width;
0125     unsigned short      out_height;
0126     uint32_t        out_pixel_fmt;
0127     unsigned short      out_stride;
0128     bool            graphics_combine_en;
0129     bool            global_alpha_en;
0130     bool            key_color_en;
0131     enum display_port   disp;
0132     unsigned short      out_left;
0133     unsigned short      out_top;
0134 };
0135
0136 /*
0137  * Union of initialization parameters for a logical channel. So far only video
0138  * parameters are used.
0139  */
0140 union ipu_channel_param {
0141     struct idmac_video_param video;
0142 };
0143
0144 struct idmac_tx_desc {
0145     struct dma_async_tx_descriptor  txd;
0146     struct scatterlist      *sg;    /* scatterlist for this */
0147     unsigned int            sg_len; /* tx-descriptor. */
0148     struct list_head        list;
0149 };
0150
0151 struct idmac_channel {
0152     struct dma_chan     dma_chan;
0153     dma_cookie_t        completed;  /* last completed cookie       */
0154     union ipu_channel_param params;
0155     enum ipu_channel    link;   /* input channel, linked to the output     */
0156     enum ipu_channel_status status;
0157     void            *client;    /* Only one client per channel     */
0158     unsigned int        n_tx_desc;
0159     struct idmac_tx_desc    *desc;      /* allocated tx-descriptors    */
0160     struct scatterlist  *sg[2]; /* scatterlist elements in buffer-0 and -1 */
0161     struct list_head    free_list;  /* free tx-descriptors         */
0162     struct list_head    queue;      /* queued tx-descriptors       */
0163     spinlock_t      lock;       /* protects sg[0,1], queue     */
0164     struct mutex        chan_mutex; /* protects status, cookie, free_list  */
0165     bool            sec_chan_en;
0166     int         active_buffer;
0167     unsigned int        eof_irq;
0168     char            eof_name[16];   /* EOF IRQ name for request_irq()  */
0169 };
0170
0171 #define to_tx_desc(tx) container_of(tx, struct idmac_tx_desc, txd)
0172 #define to_idmac_chan(c) container_of(c, struct idmac_channel, dma_chan)
0173
0174 #endif /* __LINUX_DMA_IPU_DMA_H */