Back to home page

OSCL-LXR

 
 

    


0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
0004  */
0005 
0006 #ifndef __LINUX_DMA_IMX_H
0007 #define __LINUX_DMA_IMX_H
0008 
0009 #include <linux/scatterlist.h>
0010 #include <linux/device.h>
0011 #include <linux/dmaengine.h>
0012 
0013 /*
0014  * This enumerates peripheral types. Used for SDMA.
0015  */
0016 enum sdma_peripheral_type {
0017     IMX_DMATYPE_SSI,    /* MCU domain SSI */
0018     IMX_DMATYPE_SSI_SP, /* Shared SSI */
0019     IMX_DMATYPE_MMC,    /* MMC */
0020     IMX_DMATYPE_SDHC,   /* SDHC */
0021     IMX_DMATYPE_UART,   /* MCU domain UART */
0022     IMX_DMATYPE_UART_SP,    /* Shared UART */
0023     IMX_DMATYPE_FIRI,   /* FIRI */
0024     IMX_DMATYPE_CSPI,   /* MCU domain CSPI */
0025     IMX_DMATYPE_CSPI_SP,    /* Shared CSPI */
0026     IMX_DMATYPE_SIM,    /* SIM */
0027     IMX_DMATYPE_ATA,    /* ATA */
0028     IMX_DMATYPE_CCM,    /* CCM */
0029     IMX_DMATYPE_EXT,    /* External peripheral */
0030     IMX_DMATYPE_MSHC,   /* Memory Stick Host Controller */
0031     IMX_DMATYPE_MSHC_SP,    /* Shared Memory Stick Host Controller */
0032     IMX_DMATYPE_DSP,    /* DSP */
0033     IMX_DMATYPE_MEMORY, /* Memory */
0034     IMX_DMATYPE_FIFO_MEMORY,/* FIFO type Memory */
0035     IMX_DMATYPE_SPDIF,  /* SPDIF */
0036     IMX_DMATYPE_IPU_MEMORY, /* IPU Memory */
0037     IMX_DMATYPE_ASRC,   /* ASRC */
0038     IMX_DMATYPE_ESAI,   /* ESAI */
0039     IMX_DMATYPE_SSI_DUAL,   /* SSI Dual FIFO */
0040     IMX_DMATYPE_ASRC_SP,    /* Shared ASRC */
0041     IMX_DMATYPE_SAI,    /* SAI */
0042     IMX_DMATYPE_MULTI_SAI,  /* MULTI FIFOs For Audio */
0043 };
0044 
0045 enum imx_dma_prio {
0046     DMA_PRIO_HIGH = 0,
0047     DMA_PRIO_MEDIUM = 1,
0048     DMA_PRIO_LOW = 2
0049 };
0050 
0051 struct imx_dma_data {
0052     int dma_request; /* DMA request line */
0053     int dma_request2; /* secondary DMA request line */
0054     enum sdma_peripheral_type peripheral_type;
0055     int priority;
0056 };
0057 
0058 static inline int imx_dma_is_ipu(struct dma_chan *chan)
0059 {
0060     return !strcmp(dev_name(chan->device->dev), "ipu-core");
0061 }
0062 
0063 static inline int imx_dma_is_general_purpose(struct dma_chan *chan)
0064 {
0065     return !strcmp(chan->device->dev->driver->name, "imx-sdma") ||
0066         !strcmp(chan->device->dev->driver->name, "imx-dma");
0067 }
0068 
0069 /**
0070  * struct sdma_peripheral_config - SDMA config for audio
0071  * @n_fifos_src: Number of FIFOs for recording
0072  * @n_fifos_dst: Number of FIFOs for playback
0073  * @stride_fifos_src: FIFO address stride for recording, 0 means all FIFOs are
0074  *                    continuous, 1 means 1 word stride between FIFOs. All stride
0075  *                    between FIFOs should be same.
0076  * @stride_fifos_dst: FIFO address stride for playback
0077  * @words_per_fifo: numbers of words per FIFO fetch/fill, 1 means
0078  *                  one channel per FIFO, 2 means 2 channels per FIFO..
0079  *                  If 'n_fifos_src =  4' and 'words_per_fifo = 2', it
0080  *                  means the first two words(channels) fetch from FIFO0
0081  *                  and then jump to FIFO1 for next two words, and so on
0082  *                  after the last FIFO3 fetched, roll back to FIFO0.
0083  * @sw_done: Use software done. Needed for PDM (micfil)
0084  *
0085  * Some i.MX Audio devices (SAI, micfil) have multiple successive FIFO
0086  * registers. For multichannel recording/playback the SAI/micfil have
0087  * one FIFO register per channel and the SDMA engine has to read/write
0088  * the next channel from/to the next register and wrap around to the
0089  * first register when all channels are handled. The number of active
0090  * channels must be communicated to the SDMA engine using this struct.
0091  */
0092 struct sdma_peripheral_config {
0093     int n_fifos_src;
0094     int n_fifos_dst;
0095     int stride_fifos_src;
0096     int stride_fifos_dst;
0097     int words_per_fifo;
0098     bool sw_done;
0099 };
0100 
0101 #endif /* __LINUX_DMA_IMX_H */