include/linux/cs5535.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * AMD CS5535/CS5536 definitions
0004  * Copyright (C) 2006  Advanced Micro Devices, Inc.
0005  * Copyright (C) 2009  Andres Salomon <dilinger@collabora.co.uk>
0006  */
0007
0008 #ifndef _CS5535_H
0009 #define _CS5535_H
0010
0011 #include <asm/msr.h>
0012
0013 /* MSRs */
0014 #define MSR_GLIU_P2D_RO0    0x10000029
0015
0016 #define MSR_LX_GLD_MSR_CONFIG   0x48002001
0017 #define MSR_LX_MSR_PADSEL   0x48002011  /* NOT 0x48000011; the data
0018                          * sheet has the wrong value */
0019 #define MSR_GLCP_SYS_RSTPLL 0x4C000014
0020 #define MSR_GLCP_DOTPLL     0x4C000015
0021
0022 #define MSR_LBAR_SMB        0x5140000B
0023 #define MSR_LBAR_GPIO       0x5140000C
0024 #define MSR_LBAR_MFGPT      0x5140000D
0025 #define MSR_LBAR_ACPI       0x5140000E
0026 #define MSR_LBAR_PMS        0x5140000F
0027
0028 #define MSR_DIVIL_SOFT_RESET    0x51400017
0029
0030 #define MSR_PIC_YSEL_LOW    0x51400020
0031 #define MSR_PIC_YSEL_HIGH   0x51400021
0032 #define MSR_PIC_ZSEL_LOW    0x51400022
0033 #define MSR_PIC_ZSEL_HIGH   0x51400023
0034 #define MSR_PIC_IRQM_LPC    0x51400025
0035
0036 #define MSR_MFGPT_IRQ       0x51400028
0037 #define MSR_MFGPT_NR        0x51400029
0038 #define MSR_MFGPT_SETUP     0x5140002B
0039
0040 #define MSR_RTC_DOMA_OFFSET 0x51400055
0041 #define MSR_RTC_MONA_OFFSET 0x51400056
0042 #define MSR_RTC_CEN_OFFSET  0x51400057
0043
0044 #define MSR_LX_SPARE_MSR    0x80000011  /* DC-specific */
0045
0046 #define MSR_GX_GLD_MSR_CONFIG   0xC0002001
0047 #define MSR_GX_MSR_PADSEL   0xC0002011
0048
0049 static inline int cs5535_pic_unreqz_select_high(unsigned int group,
0050                         unsigned int irq)
0051 {
0052     uint32_t lo, hi;
0053
0054     rdmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
0055     lo &= ~(0xF << (group * 4));
0056     lo |= (irq & 0xF) << (group * 4);
0057     wrmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
0058     return 0;
0059 }
0060
0061 /* PIC registers */
0062 #define CS5536_PIC_INT_SEL1 0x4d0
0063 #define CS5536_PIC_INT_SEL2 0x4d1
0064
0065 /* resource sizes */
0066 #define LBAR_GPIO_SIZE      0xFF
0067 #define LBAR_MFGPT_SIZE     0x40
0068 #define LBAR_ACPI_SIZE      0x40
0069 #define LBAR_PMS_SIZE       0x80
0070
0071 /*
0072  * PMC registers (PMS block)
0073  * It is only safe to access these registers as dword accesses.
0074  * See CS5536 Specification Update erratas 17 & 18
0075  */
0076 #define CS5536_PM_SCLK      0x10
0077 #define CS5536_PM_IN_SLPCTL 0x20
0078 #define CS5536_PM_WKXD      0x34
0079 #define CS5536_PM_WKD       0x30
0080 #define CS5536_PM_SSC       0x54
0081
0082 /*
0083  * PM registers (ACPI block)
0084  * It is only safe to access these registers as dword accesses.
0085  * See CS5536 Specification Update erratas 17 & 18
0086  */
0087 #define CS5536_PM1_STS      0x00
0088 #define CS5536_PM1_EN       0x02
0089 #define CS5536_PM1_CNT      0x08
0090 #define CS5536_PM_GPE0_STS  0x18
0091 #define CS5536_PM_GPE0_EN   0x1c
0092
0093 /* CS5536_PM1_STS bits */
0094 #define CS5536_WAK_FLAG     (1 << 15)
0095 #define CS5536_RTC_FLAG     (1 << 10)
0096 #define CS5536_PWRBTN_FLAG  (1 << 8)
0097
0098 /* CS5536_PM1_EN bits */
0099 #define CS5536_PM_PWRBTN    (1 << 8)
0100 #define CS5536_PM_RTC       (1 << 10)
0101
0102 /* CS5536_PM_GPE0_STS bits */
0103 #define CS5536_GPIOM7_PME_FLAG  (1 << 31)
0104 #define CS5536_GPIOM6_PME_FLAG  (1 << 30)
0105
0106 /* CS5536_PM_GPE0_EN bits */
0107 #define CS5536_GPIOM7_PME_EN    (1 << 31)
0108 #define CS5536_GPIOM6_PME_EN    (1 << 30)
0109
0110 /* VSA2 magic values */
0111 #define VSA_VRC_INDEX       0xAC1C
0112 #define VSA_VRC_DATA        0xAC1E
0113 #define VSA_VR_UNLOCK       0xFC53  /* unlock virtual register */
0114 #define VSA_VR_SIGNATURE    0x0003
0115 #define VSA_VR_MEM_SIZE     0x0200
0116 #define AMD_VSA_SIG     0x4132  /* signature is ascii 'VSA2' */
0117 #define GSW_VSA_SIG     0x534d  /* General Software signature */
0118
0119 #include <linux/io.h>
0120
0121 static inline int cs5535_has_vsa2(void)
0122 {
0123     static int has_vsa2 = -1;
0124
0125     if (has_vsa2 == -1) {
0126         uint16_t val;
0127
0128         /*
0129          * The VSA has virtual registers that we can query for a
0130          * signature.
0131          */
0132         outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
0133         outw(VSA_VR_SIGNATURE, VSA_VRC_INDEX);
0134
0135         val = inw(VSA_VRC_DATA);
0136         has_vsa2 = (val == AMD_VSA_SIG || val == GSW_VSA_SIG);
0137     }
0138
0139     return has_vsa2;
0140 }
0141
0142 /* GPIOs */
0143 #define GPIO_OUTPUT_VAL     0x00
0144 #define GPIO_OUTPUT_ENABLE  0x04
0145 #define GPIO_OUTPUT_OPEN_DRAIN  0x08
0146 #define GPIO_OUTPUT_INVERT  0x0C
0147 #define GPIO_OUTPUT_AUX1    0x10
0148 #define GPIO_OUTPUT_AUX2    0x14
0149 #define GPIO_PULL_UP        0x18
0150 #define GPIO_PULL_DOWN      0x1C
0151 #define GPIO_INPUT_ENABLE   0x20
0152 #define GPIO_INPUT_INVERT   0x24
0153 #define GPIO_INPUT_FILTER   0x28
0154 #define GPIO_INPUT_EVENT_COUNT  0x2C
0155 #define GPIO_READ_BACK      0x30
0156 #define GPIO_INPUT_AUX1     0x34
0157 #define GPIO_EVENTS_ENABLE  0x38
0158 #define GPIO_LOCK_ENABLE    0x3C
0159 #define GPIO_POSITIVE_EDGE_EN   0x40
0160 #define GPIO_NEGATIVE_EDGE_EN   0x44
0161 #define GPIO_POSITIVE_EDGE_STS  0x48
0162 #define GPIO_NEGATIVE_EDGE_STS  0x4C
0163
0164 #define GPIO_FLTR7_AMOUNT   0xD8
0165
0166 #define GPIO_MAP_X      0xE0
0167 #define GPIO_MAP_Y      0xE4
0168 #define GPIO_MAP_Z      0xE8
0169 #define GPIO_MAP_W      0xEC
0170
0171 #define GPIO_FE7_SEL        0xF7
0172
0173 void cs5535_gpio_set(unsigned offset, unsigned int reg);
0174 void cs5535_gpio_clear(unsigned offset, unsigned int reg);
0175 int cs5535_gpio_isset(unsigned offset, unsigned int reg);
0176 int cs5535_gpio_set_irq(unsigned group, unsigned irq);
0177 void cs5535_gpio_setup_event(unsigned offset, int pair, int pme);
0178
0179 /* MFGPTs */
0180
0181 #define MFGPT_MAX_TIMERS    8
0182 #define MFGPT_TIMER_ANY     (-1)
0183
0184 #define MFGPT_DOMAIN_WORKING    1
0185 #define MFGPT_DOMAIN_STANDBY    2
0186 #define MFGPT_DOMAIN_ANY    (MFGPT_DOMAIN_WORKING | MFGPT_DOMAIN_STANDBY)
0187
0188 #define MFGPT_CMP1      0
0189 #define MFGPT_CMP2      1
0190
0191 #define MFGPT_EVENT_IRQ     0
0192 #define MFGPT_EVENT_NMI     1
0193 #define MFGPT_EVENT_RESET   3
0194
0195 #define MFGPT_REG_CMP1      0
0196 #define MFGPT_REG_CMP2      2
0197 #define MFGPT_REG_COUNTER   4
0198 #define MFGPT_REG_SETUP     6
0199
0200 #define MFGPT_SETUP_CNTEN   (1 << 15)
0201 #define MFGPT_SETUP_CMP2    (1 << 14)
0202 #define MFGPT_SETUP_CMP1    (1 << 13)
0203 #define MFGPT_SETUP_SETUP   (1 << 12)
0204 #define MFGPT_SETUP_STOPEN  (1 << 11)
0205 #define MFGPT_SETUP_EXTEN   (1 << 10)
0206 #define MFGPT_SETUP_REVEN   (1 << 5)
0207 #define MFGPT_SETUP_CLKSEL  (1 << 4)
0208
0209 struct cs5535_mfgpt_timer;
0210
0211 extern uint16_t cs5535_mfgpt_read(struct cs5535_mfgpt_timer *timer,
0212         uint16_t reg);
0213 extern void cs5535_mfgpt_write(struct cs5535_mfgpt_timer *timer, uint16_t reg,
0214         uint16_t value);
0215
0216 extern int cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer *timer, int cmp,
0217         int event, int enable);
0218 extern int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp,
0219         int *irq, int enable);
0220 extern struct cs5535_mfgpt_timer *cs5535_mfgpt_alloc_timer(int timer,
0221         int domain);
0222 extern void cs5535_mfgpt_free_timer(struct cs5535_mfgpt_timer *timer);
0223
0224 static inline int cs5535_mfgpt_setup_irq(struct cs5535_mfgpt_timer *timer,
0225         int cmp, int *irq)
0226 {
0227     return cs5535_mfgpt_set_irq(timer, cmp, irq, 1);
0228 }
0229
0230 static inline int cs5535_mfgpt_release_irq(struct cs5535_mfgpt_timer *timer,
0231         int cmp, int *irq)
0232 {
0233     return cs5535_mfgpt_set_irq(timer, cmp, irq, 0);
0234 }
0235
0236 #endif