include/linux/cper.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * UEFI Common Platform Error Record
0004  *
0005  * Copyright (C) 2010, Intel Corp.
0006  *  Author: Huang Ying <ying.huang@intel.com>
0007  */
0008
0009 #ifndef LINUX_CPER_H
0010 #define LINUX_CPER_H
0011
0012 #include <linux/uuid.h>
0013 #include <linux/trace_seq.h>
0014
0015 /* CPER record signature and the size */
0016 #define CPER_SIG_RECORD             "CPER"
0017 #define CPER_SIG_SIZE               4
0018 /* Used in signature_end field in struct cper_record_header */
0019 #define CPER_SIG_END                0xffffffff
0020
0021 /*
0022  * CPER record header revision, used in revision field in struct
0023  * cper_record_header
0024  */
0025 #define CPER_RECORD_REV             0x0100
0026
0027 /*
0028  * CPER record length contains the CPER fields which are relevant for further
0029  * handling of a memory error in userspace (we don't carry all the fields
0030  * defined in the UEFI spec because some of them don't make any sense.)
0031  * Currently, a length of 256 should be more than enough.
0032  */
0033 #define CPER_REC_LEN                    256
0034 /*
0035  * Severity definition for error_severity in struct cper_record_header
0036  * and section_severity in struct cper_section_descriptor
0037  */
0038 enum {
0039     CPER_SEV_RECOVERABLE,
0040     CPER_SEV_FATAL,
0041     CPER_SEV_CORRECTED,
0042     CPER_SEV_INFORMATIONAL,
0043 };
0044
0045 /*
0046  * Validation bits definition for validation_bits in struct
0047  * cper_record_header. If set, corresponding fields in struct
0048  * cper_record_header contain valid information.
0049  */
0050 #define CPER_VALID_PLATFORM_ID          0x0001
0051 #define CPER_VALID_TIMESTAMP            0x0002
0052 #define CPER_VALID_PARTITION_ID         0x0004
0053
0054 /*
0055  * Notification type used to generate error record, used in
0056  * notification_type in struct cper_record_header.  These UUIDs are defined
0057  * in the UEFI spec v2.7, sec N.2.1.
0058  */
0059
0060 /* Corrected Machine Check */
0061 #define CPER_NOTIFY_CMC                         \
0062     GUID_INIT(0x2DCE8BB1, 0xBDD7, 0x450e, 0xB9, 0xAD, 0x9C, 0xF4,   \
0063           0xEB, 0xD4, 0xF8, 0x90)
0064 /* Corrected Platform Error */
0065 #define CPER_NOTIFY_CPE                         \
0066     GUID_INIT(0x4E292F96, 0xD843, 0x4a55, 0xA8, 0xC2, 0xD4, 0x81,   \
0067           0xF2, 0x7E, 0xBE, 0xEE)
0068 /* Machine Check Exception */
0069 #define CPER_NOTIFY_MCE                         \
0070     GUID_INIT(0xE8F56FFE, 0x919C, 0x4cc5, 0xBA, 0x88, 0x65, 0xAB,   \
0071           0xE1, 0x49, 0x13, 0xBB)
0072 /* PCI Express Error */
0073 #define CPER_NOTIFY_PCIE                        \
0074     GUID_INIT(0xCF93C01F, 0x1A16, 0x4dfc, 0xB8, 0xBC, 0x9C, 0x4D,   \
0075           0xAF, 0x67, 0xC1, 0x04)
0076 /* INIT Record (for IPF) */
0077 #define CPER_NOTIFY_INIT                        \
0078     GUID_INIT(0xCC5263E8, 0x9308, 0x454a, 0x89, 0xD0, 0x34, 0x0B,   \
0079           0xD3, 0x9B, 0xC9, 0x8E)
0080 /* Non-Maskable Interrupt */
0081 #define CPER_NOTIFY_NMI                         \
0082     GUID_INIT(0x5BAD89FF, 0xB7E6, 0x42c9, 0x81, 0x4A, 0xCF, 0x24,   \
0083           0x85, 0xD6, 0xE9, 0x8A)
0084 /* BOOT Error Record */
0085 #define CPER_NOTIFY_BOOT                        \
0086     GUID_INIT(0x3D61A466, 0xAB40, 0x409a, 0xA6, 0x98, 0xF3, 0x62,   \
0087           0xD4, 0x64, 0xB3, 0x8F)
0088 /* DMA Remapping Error */
0089 #define CPER_NOTIFY_DMAR                        \
0090     GUID_INIT(0x667DD791, 0xC6B3, 0x4c27, 0x8A, 0x6B, 0x0F, 0x8E,   \
0091           0x72, 0x2D, 0xEB, 0x41)
0092
0093 /*
0094  * Flags bits definitions for flags in struct cper_record_header
0095  * If set, the error has been recovered
0096  */
0097 #define CPER_HW_ERROR_FLAGS_RECOVERED       0x1
0098 /* If set, the error is for previous boot */
0099 #define CPER_HW_ERROR_FLAGS_PREVERR     0x2
0100 /* If set, the error is injected for testing */
0101 #define CPER_HW_ERROR_FLAGS_SIMULATED       0x4
0102
0103 /*
0104  * CPER section header revision, used in revision field in struct
0105  * cper_section_descriptor
0106  */
0107 #define CPER_SEC_REV                0x0100
0108
0109 /*
0110  * Validation bits definition for validation_bits in struct
0111  * cper_section_descriptor. If set, corresponding fields in struct
0112  * cper_section_descriptor contain valid information.
0113  */
0114 #define CPER_SEC_VALID_FRU_ID           0x1
0115 #define CPER_SEC_VALID_FRU_TEXT         0x2
0116
0117 /*
0118  * Flags bits definitions for flags in struct cper_section_descriptor
0119  *
0120  * If set, the section is associated with the error condition
0121  * directly, and should be focused on
0122  */
0123 #define CPER_SEC_PRIMARY            0x0001
0124 /*
0125  * If set, the error was not contained within the processor or memory
0126  * hierarchy and the error may have propagated to persistent storage
0127  * or network
0128  */
0129 #define CPER_SEC_CONTAINMENT_WARNING        0x0002
0130 /* If set, the component must be re-initialized or re-enabled prior to use */
0131 #define CPER_SEC_RESET              0x0004
0132 /* If set, Linux may choose to discontinue use of the resource */
0133 #define CPER_SEC_ERROR_THRESHOLD_EXCEEDED   0x0008
0134 /*
0135  * If set, resource could not be queried for error information due to
0136  * conflicts with other system software or resources. Some fields of
0137  * the section will be invalid
0138  */
0139 #define CPER_SEC_RESOURCE_NOT_ACCESSIBLE    0x0010
0140 /*
0141  * If set, action has been taken to ensure error containment (such as
0142  * poisoning data), but the error has not been fully corrected and the
0143  * data has not been consumed. Linux may choose to take further
0144  * corrective action before the data is consumed
0145  */
0146 #define CPER_SEC_LATENT_ERROR           0x0020
0147
0148 /*
0149  * Section type definitions, used in section_type field in struct
0150  * cper_section_descriptor.  These UUIDs are defined in the UEFI spec
0151  * v2.7, sec N.2.2.
0152  */
0153
0154 /* Processor Generic */
0155 #define CPER_SEC_PROC_GENERIC                       \
0156     GUID_INIT(0x9876CCAD, 0x47B4, 0x4bdb, 0xB6, 0x5E, 0x16, 0xF1,   \
0157           0x93, 0xC4, 0xF3, 0xDB)
0158 /* Processor Specific: X86/X86_64 */
0159 #define CPER_SEC_PROC_IA                        \
0160     GUID_INIT(0xDC3EA0B0, 0xA144, 0x4797, 0xB9, 0x5B, 0x53, 0xFA,   \
0161           0x24, 0x2B, 0x6E, 0x1D)
0162 /* Processor Specific: IA64 */
0163 #define CPER_SEC_PROC_IPF                       \
0164     GUID_INIT(0xE429FAF1, 0x3CB7, 0x11D4, 0x0B, 0xCA, 0x07, 0x00,   \
0165           0x80, 0xC7, 0x3C, 0x88, 0x81)
0166 /* Processor Specific: ARM */
0167 #define CPER_SEC_PROC_ARM                       \
0168     GUID_INIT(0xE19E3D16, 0xBC11, 0x11E4, 0x9C, 0xAA, 0xC2, 0x05,   \
0169           0x1D, 0x5D, 0x46, 0xB0)
0170 /* Platform Memory */
0171 #define CPER_SEC_PLATFORM_MEM                       \
0172     GUID_INIT(0xA5BC1114, 0x6F64, 0x4EDE, 0xB8, 0x63, 0x3E, 0x83,   \
0173           0xED, 0x7C, 0x83, 0xB1)
0174 #define CPER_SEC_PCIE                           \
0175     GUID_INIT(0xD995E954, 0xBBC1, 0x430F, 0xAD, 0x91, 0xB4, 0x4D,   \
0176           0xCB, 0x3C, 0x6F, 0x35)
0177 /* Firmware Error Record Reference */
0178 #define CPER_SEC_FW_ERR_REC_REF                     \
0179     GUID_INIT(0x81212A96, 0x09ED, 0x4996, 0x94, 0x71, 0x8D, 0x72,   \
0180           0x9C, 0x8E, 0x69, 0xED)
0181 /* PCI/PCI-X Bus */
0182 #define CPER_SEC_PCI_X_BUS                      \
0183     GUID_INIT(0xC5753963, 0x3B84, 0x4095, 0xBF, 0x78, 0xED, 0xDA,   \
0184           0xD3, 0xF9, 0xC9, 0xDD)
0185 /* PCI Component/Device */
0186 #define CPER_SEC_PCI_DEV                        \
0187     GUID_INIT(0xEB5E4685, 0xCA66, 0x4769, 0xB6, 0xA2, 0x26, 0x06,   \
0188           0x8B, 0x00, 0x13, 0x26)
0189 #define CPER_SEC_DMAR_GENERIC                       \
0190     GUID_INIT(0x5B51FEF7, 0xC79D, 0x4434, 0x8F, 0x1B, 0xAA, 0x62,   \
0191           0xDE, 0x3E, 0x2C, 0x64)
0192 /* Intel VT for Directed I/O specific DMAr */
0193 #define CPER_SEC_DMAR_VT                        \
0194     GUID_INIT(0x71761D37, 0x32B2, 0x45cd, 0xA7, 0xD0, 0xB0, 0xFE,   \
0195           0xDD, 0x93, 0xE8, 0xCF)
0196 /* IOMMU specific DMAr */
0197 #define CPER_SEC_DMAR_IOMMU                     \
0198     GUID_INIT(0x036F84E1, 0x7F37, 0x428c, 0xA7, 0x9E, 0x57, 0x5F,   \
0199           0xDF, 0xAA, 0x84, 0xEC)
0200
0201 #define CPER_PROC_VALID_TYPE            0x0001
0202 #define CPER_PROC_VALID_ISA         0x0002
0203 #define CPER_PROC_VALID_ERROR_TYPE      0x0004
0204 #define CPER_PROC_VALID_OPERATION       0x0008
0205 #define CPER_PROC_VALID_FLAGS           0x0010
0206 #define CPER_PROC_VALID_LEVEL           0x0020
0207 #define CPER_PROC_VALID_VERSION         0x0040
0208 #define CPER_PROC_VALID_BRAND_INFO      0x0080
0209 #define CPER_PROC_VALID_ID          0x0100
0210 #define CPER_PROC_VALID_TARGET_ADDRESS      0x0200
0211 #define CPER_PROC_VALID_REQUESTOR_ID        0x0400
0212 #define CPER_PROC_VALID_RESPONDER_ID        0x0800
0213 #define CPER_PROC_VALID_IP          0x1000
0214
0215 #define CPER_MEM_VALID_ERROR_STATUS     0x0001
0216 #define CPER_MEM_VALID_PA           0x0002
0217 #define CPER_MEM_VALID_PA_MASK          0x0004
0218 #define CPER_MEM_VALID_NODE         0x0008
0219 #define CPER_MEM_VALID_CARD         0x0010
0220 #define CPER_MEM_VALID_MODULE           0x0020
0221 #define CPER_MEM_VALID_BANK         0x0040
0222 #define CPER_MEM_VALID_DEVICE           0x0080
0223 #define CPER_MEM_VALID_ROW          0x0100
0224 #define CPER_MEM_VALID_COLUMN           0x0200
0225 #define CPER_MEM_VALID_BIT_POSITION     0x0400
0226 #define CPER_MEM_VALID_REQUESTOR_ID     0x0800
0227 #define CPER_MEM_VALID_RESPONDER_ID     0x1000
0228 #define CPER_MEM_VALID_TARGET_ID        0x2000
0229 #define CPER_MEM_VALID_ERROR_TYPE       0x4000
0230 #define CPER_MEM_VALID_RANK_NUMBER      0x8000
0231 #define CPER_MEM_VALID_CARD_HANDLE      0x10000
0232 #define CPER_MEM_VALID_MODULE_HANDLE        0x20000
0233 #define CPER_MEM_VALID_ROW_EXT          0x40000
0234 #define CPER_MEM_VALID_BANK_GROUP       0x80000
0235 #define CPER_MEM_VALID_BANK_ADDRESS     0x100000
0236 #define CPER_MEM_VALID_CHIP_ID          0x200000
0237
0238 #define CPER_MEM_EXT_ROW_MASK           0x3
0239 #define CPER_MEM_EXT_ROW_SHIFT          16
0240
0241 #define CPER_MEM_BANK_ADDRESS_MASK      0xff
0242 #define CPER_MEM_BANK_GROUP_SHIFT       8
0243
0244 #define CPER_MEM_CHIP_ID_SHIFT          5
0245
0246 #define CPER_PCIE_VALID_PORT_TYPE       0x0001
0247 #define CPER_PCIE_VALID_VERSION         0x0002
0248 #define CPER_PCIE_VALID_COMMAND_STATUS      0x0004
0249 #define CPER_PCIE_VALID_DEVICE_ID       0x0008
0250 #define CPER_PCIE_VALID_SERIAL_NUMBER       0x0010
0251 #define CPER_PCIE_VALID_BRIDGE_CONTROL_STATUS   0x0020
0252 #define CPER_PCIE_VALID_CAPABILITY      0x0040
0253 #define CPER_PCIE_VALID_AER_INFO        0x0080
0254
0255 #define CPER_PCIE_SLOT_SHIFT            3
0256
0257 #define CPER_ARM_VALID_MPIDR            BIT(0)
0258 #define CPER_ARM_VALID_AFFINITY_LEVEL       BIT(1)
0259 #define CPER_ARM_VALID_RUNNING_STATE        BIT(2)
0260 #define CPER_ARM_VALID_VENDOR_INFO      BIT(3)
0261
0262 #define CPER_ARM_INFO_VALID_MULTI_ERR       BIT(0)
0263 #define CPER_ARM_INFO_VALID_FLAGS       BIT(1)
0264 #define CPER_ARM_INFO_VALID_ERR_INFO        BIT(2)
0265 #define CPER_ARM_INFO_VALID_VIRT_ADDR       BIT(3)
0266 #define CPER_ARM_INFO_VALID_PHYSICAL_ADDR   BIT(4)
0267
0268 #define CPER_ARM_INFO_FLAGS_FIRST       BIT(0)
0269 #define CPER_ARM_INFO_FLAGS_LAST        BIT(1)
0270 #define CPER_ARM_INFO_FLAGS_PROPAGATED      BIT(2)
0271 #define CPER_ARM_INFO_FLAGS_OVERFLOW        BIT(3)
0272
0273 #define CPER_ARM_CACHE_ERROR            0
0274 #define CPER_ARM_TLB_ERROR          1
0275 #define CPER_ARM_BUS_ERROR          2
0276 #define CPER_ARM_VENDOR_ERROR           3
0277 #define CPER_ARM_MAX_TYPE           CPER_ARM_VENDOR_ERROR
0278
0279 #define CPER_ARM_ERR_VALID_TRANSACTION_TYPE BIT(0)
0280 #define CPER_ARM_ERR_VALID_OPERATION_TYPE   BIT(1)
0281 #define CPER_ARM_ERR_VALID_LEVEL        BIT(2)
0282 #define CPER_ARM_ERR_VALID_PROC_CONTEXT_CORRUPT BIT(3)
0283 #define CPER_ARM_ERR_VALID_CORRECTED        BIT(4)
0284 #define CPER_ARM_ERR_VALID_PRECISE_PC       BIT(5)
0285 #define CPER_ARM_ERR_VALID_RESTARTABLE_PC   BIT(6)
0286 #define CPER_ARM_ERR_VALID_PARTICIPATION_TYPE   BIT(7)
0287 #define CPER_ARM_ERR_VALID_TIME_OUT     BIT(8)
0288 #define CPER_ARM_ERR_VALID_ADDRESS_SPACE    BIT(9)
0289 #define CPER_ARM_ERR_VALID_MEM_ATTRIBUTES   BIT(10)
0290 #define CPER_ARM_ERR_VALID_ACCESS_MODE      BIT(11)
0291
0292 #define CPER_ARM_ERR_TRANSACTION_SHIFT      16
0293 #define CPER_ARM_ERR_TRANSACTION_MASK       GENMASK(1,0)
0294 #define CPER_ARM_ERR_OPERATION_SHIFT        18
0295 #define CPER_ARM_ERR_OPERATION_MASK     GENMASK(3,0)
0296 #define CPER_ARM_ERR_LEVEL_SHIFT        22
0297 #define CPER_ARM_ERR_LEVEL_MASK         GENMASK(2,0)
0298 #define CPER_ARM_ERR_PC_CORRUPT_SHIFT       25
0299 #define CPER_ARM_ERR_PC_CORRUPT_MASK        GENMASK(0,0)
0300 #define CPER_ARM_ERR_CORRECTED_SHIFT        26
0301 #define CPER_ARM_ERR_CORRECTED_MASK     GENMASK(0,0)
0302 #define CPER_ARM_ERR_PRECISE_PC_SHIFT       27
0303 #define CPER_ARM_ERR_PRECISE_PC_MASK        GENMASK(0,0)
0304 #define CPER_ARM_ERR_RESTARTABLE_PC_SHIFT   28
0305 #define CPER_ARM_ERR_RESTARTABLE_PC_MASK    GENMASK(0,0)
0306 #define CPER_ARM_ERR_PARTICIPATION_TYPE_SHIFT   29
0307 #define CPER_ARM_ERR_PARTICIPATION_TYPE_MASK    GENMASK(1,0)
0308 #define CPER_ARM_ERR_TIME_OUT_SHIFT     31
0309 #define CPER_ARM_ERR_TIME_OUT_MASK      GENMASK(0,0)
0310 #define CPER_ARM_ERR_ADDRESS_SPACE_SHIFT    32
0311 #define CPER_ARM_ERR_ADDRESS_SPACE_MASK     GENMASK(1,0)
0312 #define CPER_ARM_ERR_MEM_ATTRIBUTES_SHIFT   34
0313 #define CPER_ARM_ERR_MEM_ATTRIBUTES_MASK    GENMASK(8,0)
0314 #define CPER_ARM_ERR_ACCESS_MODE_SHIFT      43
0315 #define CPER_ARM_ERR_ACCESS_MODE_MASK       GENMASK(0,0)
0316
0317 /*
0318  * All tables and structs must be byte-packed to match CPER
0319  * specification, since the tables are provided by the system BIOS
0320  */
0321 #pragma pack(1)
0322
0323 /* Record Header, UEFI v2.7 sec N.2.1 */
0324 struct cper_record_header {
0325     char    signature[CPER_SIG_SIZE];   /* must be CPER_SIG_RECORD */
0326     u16 revision;           /* must be CPER_RECORD_REV */
0327     u32 signature_end;          /* must be CPER_SIG_END */
0328     u16 section_count;
0329     u32 error_severity;
0330     u32 validation_bits;
0331     u32 record_length;
0332     u64 timestamp;
0333     guid_t  platform_id;
0334     guid_t  partition_id;
0335     guid_t  creator_id;
0336     guid_t  notification_type;
0337     u64 record_id;
0338     u32 flags;
0339     u64 persistence_information;
0340     u8  reserved[12];           /* must be zero */
0341 };
0342
0343 /* Section Descriptor, UEFI v2.7 sec N.2.2 */
0344 struct cper_section_descriptor {
0345     u32 section_offset;     /* Offset in bytes of the
0346                      *  section body from the base
0347                      *  of the record header */
0348     u32 section_length;
0349     u16 revision;       /* must be CPER_RECORD_REV */
0350     u8  validation_bits;
0351     u8  reserved;       /* must be zero */
0352     u32 flags;
0353     guid_t  section_type;
0354     guid_t  fru_id;
0355     u32 section_severity;
0356     u8  fru_text[20];
0357 };
0358
0359 /* Generic Processor Error Section, UEFI v2.7 sec N.2.4.1 */
0360 struct cper_sec_proc_generic {
0361     u64 validation_bits;
0362     u8  proc_type;
0363     u8  proc_isa;
0364     u8  proc_error_type;
0365     u8  operation;
0366     u8  flags;
0367     u8  level;
0368     u16 reserved;
0369     u64 cpu_version;
0370     char    cpu_brand[128];
0371     u64 proc_id;
0372     u64 target_addr;
0373     u64 requestor_id;
0374     u64 responder_id;
0375     u64 ip;
0376 };
0377
0378 /* IA32/X64 Processor Error Section, UEFI v2.7 sec N.2.4.2 */
0379 struct cper_sec_proc_ia {
0380     u64 validation_bits;
0381     u64 lapic_id;
0382     u8  cpuid[48];
0383 };
0384
0385 /* IA32/X64 Processor Error Information Structure, UEFI v2.7 sec N.2.4.2.1 */
0386 struct cper_ia_err_info {
0387     guid_t  err_type;
0388     u64 validation_bits;
0389     u64 check_info;
0390     u64 target_id;
0391     u64 requestor_id;
0392     u64 responder_id;
0393     u64 ip;
0394 };
0395
0396 /* IA32/X64 Processor Context Information Structure, UEFI v2.7 sec N.2.4.2.2 */
0397 struct cper_ia_proc_ctx {
0398     u16 reg_ctx_type;
0399     u16 reg_arr_size;
0400     u32 msr_addr;
0401     u64 mm_reg_addr;
0402 };
0403
0404 /* ARM Processor Error Section, UEFI v2.7 sec N.2.4.4 */
0405 struct cper_sec_proc_arm {
0406     u32 validation_bits;
0407     u16 err_info_num;       /* Number of Processor Error Info */
0408     u16 context_info_num;   /* Number of Processor Context Info Records*/
0409     u32 section_length;
0410     u8  affinity_level;
0411     u8  reserved[3];        /* must be zero */
0412     u64 mpidr;
0413     u64 midr;
0414     u32 running_state;      /* Bit 0 set - Processor running. PSCI = 0 */
0415     u32 psci_state;
0416 };
0417
0418 /* ARM Processor Error Information Structure, UEFI v2.7 sec N.2.4.4.1 */
0419 struct cper_arm_err_info {
0420     u8  version;
0421     u8  length;
0422     u16 validation_bits;
0423     u8  type;
0424     u16 multiple_error;
0425     u8  flags;
0426     u64 error_info;
0427     u64 virt_fault_addr;
0428     u64 physical_fault_addr;
0429 };
0430
0431 /* ARM Processor Context Information Structure, UEFI v2.7 sec N.2.4.4.2 */
0432 struct cper_arm_ctx_info {
0433     u16 version;
0434     u16 type;
0435     u32 size;
0436 };
0437
0438 /* Old Memory Error Section, UEFI v2.1, v2.2 */
0439 struct cper_sec_mem_err_old {
0440     u64 validation_bits;
0441     u64 error_status;
0442     u64 physical_addr;
0443     u64 physical_addr_mask;
0444     u16 node;
0445     u16 card;
0446     u16 module;
0447     u16 bank;
0448     u16 device;
0449     u16 row;
0450     u16 column;
0451     u16 bit_pos;
0452     u64 requestor_id;
0453     u64 responder_id;
0454     u64 target_id;
0455     u8  error_type;
0456 };
0457
0458 /* Memory Error Section (UEFI >= v2.3), UEFI v2.8 sec N.2.5 */
0459 struct cper_sec_mem_err {
0460     u64 validation_bits;
0461     u64 error_status;
0462     u64 physical_addr;
0463     u64 physical_addr_mask;
0464     u16 node;
0465     u16 card;
0466     u16 module;
0467     u16 bank;
0468     u16 device;
0469     u16 row;
0470     u16 column;
0471     u16 bit_pos;
0472     u64 requestor_id;
0473     u64 responder_id;
0474     u64 target_id;
0475     u8  error_type;
0476     u8  extended;
0477     u16 rank;
0478     u16 mem_array_handle;   /* "card handle" in UEFI 2.4 */
0479     u16 mem_dev_handle;     /* "module handle" in UEFI 2.4 */
0480 };
0481
0482 struct cper_mem_err_compact {
0483     u64 validation_bits;
0484     u16 node;
0485     u16 card;
0486     u16 module;
0487     u16 bank;
0488     u16 device;
0489     u16 row;
0490     u16 column;
0491     u16 bit_pos;
0492     u64 requestor_id;
0493     u64 responder_id;
0494     u64 target_id;
0495     u16 rank;
0496     u16 mem_array_handle;
0497     u16 mem_dev_handle;
0498     u8      extended;
0499 };
0500
0501 static inline u32 cper_get_mem_extension(u64 mem_valid, u8 mem_extended)
0502 {
0503     if (!(mem_valid & CPER_MEM_VALID_ROW_EXT))
0504         return 0;
0505     return (mem_extended & CPER_MEM_EXT_ROW_MASK) << CPER_MEM_EXT_ROW_SHIFT;
0506 }
0507
0508 /* PCI Express Error Section, UEFI v2.7 sec N.2.7 */
0509 struct cper_sec_pcie {
0510     u64     validation_bits;
0511     u32     port_type;
0512     struct {
0513         u8  minor;
0514         u8  major;
0515         u8  reserved[2];
0516     }       version;
0517     u16     command;
0518     u16     status;
0519     u32     reserved;
0520     struct {
0521         u16 vendor_id;
0522         u16 device_id;
0523         u8  class_code[3];
0524         u8  function;
0525         u8  device;
0526         u16 segment;
0527         u8  bus;
0528         u8  secondary_bus;
0529         u16 slot;
0530         u8  reserved;
0531     }       device_id;
0532     struct {
0533         u32 lower;
0534         u32 upper;
0535     }       serial_number;
0536     struct {
0537         u16 secondary_status;
0538         u16 control;
0539     }       bridge;
0540     u8  capability[60];
0541     u8  aer_info[96];
0542 };
0543
0544 /* Firmware Error Record Reference, UEFI v2.7 sec N.2.10  */
0545 struct cper_sec_fw_err_rec_ref {
0546     u8 record_type;
0547     u8 revision;
0548     u8 reserved[6];
0549     u64 record_identifier;
0550     guid_t record_identifier_guid;
0551 };
0552
0553 /* Reset to default packing */
0554 #pragma pack()
0555
0556 extern const char *const cper_proc_error_type_strs[4];
0557
0558 u64 cper_next_record_id(void);
0559 const char *cper_severity_str(unsigned int);
0560 const char *cper_mem_err_type_str(unsigned int);
0561 const char *cper_mem_err_status_str(u64 status);
0562 void cper_print_bits(const char *prefix, unsigned int bits,
0563              const char * const strs[], unsigned int strs_size);
0564 void cper_mem_err_pack(const struct cper_sec_mem_err *,
0565                struct cper_mem_err_compact *);
0566 const char *cper_mem_err_unpack(struct trace_seq *,
0567                 struct cper_mem_err_compact *);
0568 void cper_print_proc_arm(const char *pfx,
0569              const struct cper_sec_proc_arm *proc);
0570 void cper_print_proc_ia(const char *pfx,
0571             const struct cper_sec_proc_ia *proc);
0572 int cper_mem_err_location(struct cper_mem_err_compact *mem, char *msg);
0573 int cper_dimm_err_location(struct cper_mem_err_compact *mem, char *msg);
0574
0575 #endif