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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2012, The Linux Foundation. All rights reserved.
0004  */
0005 
0006 #ifndef _LINUX_CORESIGHT_H
0007 #define _LINUX_CORESIGHT_H
0008 
0009 #include <linux/device.h>
0010 #include <linux/io.h>
0011 #include <linux/perf_event.h>
0012 #include <linux/sched.h>
0013 
0014 /* Peripheral id registers (0xFD0-0xFEC) */
0015 #define CORESIGHT_PERIPHIDR4    0xfd0
0016 #define CORESIGHT_PERIPHIDR5    0xfd4
0017 #define CORESIGHT_PERIPHIDR6    0xfd8
0018 #define CORESIGHT_PERIPHIDR7    0xfdC
0019 #define CORESIGHT_PERIPHIDR0    0xfe0
0020 #define CORESIGHT_PERIPHIDR1    0xfe4
0021 #define CORESIGHT_PERIPHIDR2    0xfe8
0022 #define CORESIGHT_PERIPHIDR3    0xfeC
0023 /* Component id registers (0xFF0-0xFFC) */
0024 #define CORESIGHT_COMPIDR0  0xff0
0025 #define CORESIGHT_COMPIDR1  0xff4
0026 #define CORESIGHT_COMPIDR2  0xff8
0027 #define CORESIGHT_COMPIDR3  0xffC
0028 
0029 #define ETM_ARCH_V3_3       0x23
0030 #define ETM_ARCH_V3_5       0x25
0031 #define PFT_ARCH_V1_0       0x30
0032 #define PFT_ARCH_V1_1       0x31
0033 
0034 #define CORESIGHT_UNLOCK    0xc5acce55
0035 
0036 extern struct bus_type coresight_bustype;
0037 
0038 enum coresight_dev_type {
0039     CORESIGHT_DEV_TYPE_SINK,
0040     CORESIGHT_DEV_TYPE_LINK,
0041     CORESIGHT_DEV_TYPE_LINKSINK,
0042     CORESIGHT_DEV_TYPE_SOURCE,
0043     CORESIGHT_DEV_TYPE_HELPER,
0044     CORESIGHT_DEV_TYPE_ECT,
0045 };
0046 
0047 enum coresight_dev_subtype_sink {
0048     CORESIGHT_DEV_SUBTYPE_SINK_PORT,
0049     CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
0050     CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM,
0051     CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM,
0052 };
0053 
0054 enum coresight_dev_subtype_link {
0055     CORESIGHT_DEV_SUBTYPE_LINK_MERG,
0056     CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
0057     CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
0058 };
0059 
0060 enum coresight_dev_subtype_source {
0061     CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
0062     CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
0063     CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
0064 };
0065 
0066 enum coresight_dev_subtype_helper {
0067     CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
0068 };
0069 
0070 /* Embedded Cross Trigger (ECT) sub-types */
0071 enum coresight_dev_subtype_ect {
0072     CORESIGHT_DEV_SUBTYPE_ECT_NONE,
0073     CORESIGHT_DEV_SUBTYPE_ECT_CTI,
0074 };
0075 
0076 /**
0077  * union coresight_dev_subtype - further characterisation of a type
0078  * @sink_subtype:   type of sink this component is, as defined
0079  *          by @coresight_dev_subtype_sink.
0080  * @link_subtype:   type of link this component is, as defined
0081  *          by @coresight_dev_subtype_link.
0082  * @source_subtype: type of source this component is, as defined
0083  *          by @coresight_dev_subtype_source.
0084  * @helper_subtype: type of helper this component is, as defined
0085  *          by @coresight_dev_subtype_helper.
0086  * @ect_subtype:        type of cross trigger this component is, as
0087  *          defined by @coresight_dev_subtype_ect
0088  */
0089 union coresight_dev_subtype {
0090     /* We have some devices which acts as LINK and SINK */
0091     struct {
0092         enum coresight_dev_subtype_sink sink_subtype;
0093         enum coresight_dev_subtype_link link_subtype;
0094     };
0095     enum coresight_dev_subtype_source source_subtype;
0096     enum coresight_dev_subtype_helper helper_subtype;
0097     enum coresight_dev_subtype_ect ect_subtype;
0098 };
0099 
0100 /**
0101  * struct coresight_platform_data - data harvested from the firmware
0102  * specification.
0103  *
0104  * @nr_inport:  Number of elements for the input connections.
0105  * @nr_outport: Number of elements for the output connections.
0106  * @conns:  Sparse array of nr_outport connections from this component.
0107  */
0108 struct coresight_platform_data {
0109     int nr_inport;
0110     int nr_outport;
0111     struct coresight_connection *conns;
0112 };
0113 
0114 /**
0115  * struct csdev_access - Abstraction of a CoreSight device access.
0116  *
0117  * @io_mem  : True if the device has memory mapped I/O
0118  * @base    : When io_mem == true, base address of the component
0119  * @read    : Read from the given "offset" of the given instance.
0120  * @write   : Write "val" to the given "offset".
0121  */
0122 struct csdev_access {
0123     bool io_mem;
0124     union {
0125         void __iomem *base;
0126         struct {
0127             u64 (*read)(u32 offset, bool relaxed, bool _64bit);
0128             void (*write)(u64 val, u32 offset, bool relaxed,
0129                       bool _64bit);
0130         };
0131     };
0132 };
0133 
0134 #define CSDEV_ACCESS_IOMEM(_addr)       \
0135     ((struct csdev_access)  {       \
0136         .io_mem     = true,     \
0137         .base       = (_addr),  \
0138     })
0139 
0140 /**
0141  * struct coresight_desc - description of a component required from drivers
0142  * @type:   as defined by @coresight_dev_type.
0143  * @subtype:    as defined by @coresight_dev_subtype.
0144  * @ops:    generic operations for this component, as defined
0145  *      by @coresight_ops.
0146  * @pdata:  platform data collected from DT.
0147  * @dev:    The device entity associated to this component.
0148  * @groups: operations specific to this component. These will end up
0149  *      in the component's sysfs sub-directory.
0150  * @name:   name for the coresight device, also shown under sysfs.
0151  * @access: Describe access to the device
0152  */
0153 struct coresight_desc {
0154     enum coresight_dev_type type;
0155     union coresight_dev_subtype subtype;
0156     const struct coresight_ops *ops;
0157     struct coresight_platform_data *pdata;
0158     struct device *dev;
0159     const struct attribute_group **groups;
0160     const char *name;
0161     struct csdev_access access;
0162 };
0163 
0164 /**
0165  * struct coresight_connection - representation of a single connection
0166  * @outport:    a connection's output port number.
0167  * @child_port: remote component's port number @output is connected to.
0168  * @chid_fwnode: remote component's fwnode handle.
0169  * @child_dev:  a @coresight_device representation of the component
0170         connected to @outport.
0171  * @link: Representation of the connection as a sysfs link.
0172  */
0173 struct coresight_connection {
0174     int outport;
0175     int child_port;
0176     struct fwnode_handle *child_fwnode;
0177     struct coresight_device *child_dev;
0178     struct coresight_sysfs_link *link;
0179 };
0180 
0181 /**
0182  * struct coresight_sysfs_link - representation of a connection in sysfs.
0183  * @orig:       Originating (master) coresight device for the link.
0184  * @orig_name:      Name to use for the link orig->target.
0185  * @target:     Target (slave) coresight device for the link.
0186  * @target_name:    Name to use for the link target->orig.
0187  */
0188 struct coresight_sysfs_link {
0189     struct coresight_device *orig;
0190     const char *orig_name;
0191     struct coresight_device *target;
0192     const char *target_name;
0193 };
0194 
0195 /**
0196  * struct coresight_device - representation of a device as used by the framework
0197  * @pdata:  Platform data with device connections associated to this device.
0198  * @type:   as defined by @coresight_dev_type.
0199  * @subtype:    as defined by @coresight_dev_subtype.
0200  * @ops:    generic operations for this component, as defined
0201  *      by @coresight_ops.
0202  * @access: Device i/o access abstraction for this device.
0203  * @dev:    The device entity associated to this component.
0204  * @refcnt: keep track of what is in use.
0205  * @orphan: true if the component has connections that haven't been linked.
0206  * @enable: 'true' if component is currently part of an active path.
0207  * @activated:  'true' only if a _sink_ has been activated.  A sink can be
0208  *      activated but not yet enabled.  Enabling for a _sink_
0209  *      happens when a source has been selected and a path is enabled
0210  *      from source to that sink.
0211  * @ea:     Device attribute for sink representation under PMU directory.
0212  * @def_sink:   cached reference to default sink found for this device.
0213  * @ect_dev:    Associated cross trigger device. Not part of the trace data
0214  *      path or connections.
0215  * @nr_links:   number of sysfs links created to other components from this
0216  *      device. These will appear in the "connections" group.
0217  * @has_conns_grp: Have added a "connections" group for sysfs links.
0218  * @feature_csdev_list: List of complex feature programming added to the device.
0219  * @config_csdev_list:  List of system configurations added to the device.
0220  * @cscfg_csdev_lock:   Protect the lists of configurations and features.
0221  * @active_cscfg_ctxt:  Context information for current active system configuration.
0222  */
0223 struct coresight_device {
0224     struct coresight_platform_data *pdata;
0225     enum coresight_dev_type type;
0226     union coresight_dev_subtype subtype;
0227     const struct coresight_ops *ops;
0228     struct csdev_access access;
0229     struct device dev;
0230     atomic_t *refcnt;
0231     bool orphan;
0232     bool enable;    /* true only if configured as part of a path */
0233     /* sink specific fields */
0234     bool activated; /* true only if a sink is part of a path */
0235     struct dev_ext_attribute *ea;
0236     struct coresight_device *def_sink;
0237     /* cross trigger handling */
0238     struct coresight_device *ect_dev;
0239     /* sysfs links between components */
0240     int nr_links;
0241     bool has_conns_grp;
0242     bool ect_enabled; /* true only if associated ect device is enabled */
0243     /* system configuration and feature lists */
0244     struct list_head feature_csdev_list;
0245     struct list_head config_csdev_list;
0246     spinlock_t cscfg_csdev_lock;
0247     void *active_cscfg_ctxt;
0248 };
0249 
0250 /*
0251  * coresight_dev_list - Mapping for devices to "name" index for device
0252  * names.
0253  *
0254  * @nr_idx:     Number of entries already allocated.
0255  * @pfx:        Prefix pattern for device name.
0256  * @fwnode_list:    Array of fwnode_handles associated with each allocated
0257  *          index, upto nr_idx entries.
0258  */
0259 struct coresight_dev_list {
0260     int         nr_idx;
0261     const char      *pfx;
0262     struct fwnode_handle    **fwnode_list;
0263 };
0264 
0265 #define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx)              \
0266 static struct coresight_dev_list (var) = {              \
0267                         .pfx = dev_pfx,     \
0268                         .nr_idx = 0,        \
0269                         .fwnode_list = NULL,    \
0270 }
0271 
0272 #define to_coresight_device(d) container_of(d, struct coresight_device, dev)
0273 
0274 #define source_ops(csdev)   csdev->ops->source_ops
0275 #define sink_ops(csdev)     csdev->ops->sink_ops
0276 #define link_ops(csdev)     csdev->ops->link_ops
0277 #define helper_ops(csdev)   csdev->ops->helper_ops
0278 #define ect_ops(csdev)      csdev->ops->ect_ops
0279 
0280 /**
0281  * struct coresight_ops_sink - basic operations for a sink
0282  * Operations available for sinks
0283  * @enable:     enables the sink.
0284  * @disable:        disables the sink.
0285  * @alloc_buffer:   initialises perf's ring buffer for trace collection.
0286  * @free_buffer:    release memory allocated in @get_config.
0287  * @update_buffer:  update buffer pointers after a trace session.
0288  */
0289 struct coresight_ops_sink {
0290     int (*enable)(struct coresight_device *csdev, u32 mode, void *data);
0291     int (*disable)(struct coresight_device *csdev);
0292     void *(*alloc_buffer)(struct coresight_device *csdev,
0293                   struct perf_event *event, void **pages,
0294                   int nr_pages, bool overwrite);
0295     void (*free_buffer)(void *config);
0296     unsigned long (*update_buffer)(struct coresight_device *csdev,
0297                   struct perf_output_handle *handle,
0298                   void *sink_config);
0299 };
0300 
0301 /**
0302  * struct coresight_ops_link - basic operations for a link
0303  * Operations available for links.
0304  * @enable: enables flow between iport and oport.
0305  * @disable:    disables flow between iport and oport.
0306  */
0307 struct coresight_ops_link {
0308     int (*enable)(struct coresight_device *csdev, int iport, int oport);
0309     void (*disable)(struct coresight_device *csdev, int iport, int oport);
0310 };
0311 
0312 /**
0313  * struct coresight_ops_source - basic operations for a source
0314  * Operations available for sources.
0315  * @cpu_id: returns the value of the CPU number this component
0316  *      is associated to.
0317  * @trace_id:   returns the value of the component's trace ID as known
0318  *      to the HW.
0319  * @enable: enables tracing for a source.
0320  * @disable:    disables tracing for a source.
0321  */
0322 struct coresight_ops_source {
0323     int (*cpu_id)(struct coresight_device *csdev);
0324     int (*trace_id)(struct coresight_device *csdev);
0325     int (*enable)(struct coresight_device *csdev,
0326               struct perf_event *event,  u32 mode);
0327     void (*disable)(struct coresight_device *csdev,
0328             struct perf_event *event);
0329 };
0330 
0331 /**
0332  * struct coresight_ops_helper - Operations for a helper device.
0333  *
0334  * All operations could pass in a device specific data, which could
0335  * help the helper device to determine what to do.
0336  *
0337  * @enable  : Enable the device
0338  * @disable : Disable the device
0339  */
0340 struct coresight_ops_helper {
0341     int (*enable)(struct coresight_device *csdev, void *data);
0342     int (*disable)(struct coresight_device *csdev, void *data);
0343 };
0344 
0345 /**
0346  * struct coresight_ops_ect - Ops for an embedded cross trigger device
0347  *
0348  * @enable  : Enable the device
0349  * @disable : Disable the device
0350  */
0351 struct coresight_ops_ect {
0352     int (*enable)(struct coresight_device *csdev);
0353     int (*disable)(struct coresight_device *csdev);
0354 };
0355 
0356 struct coresight_ops {
0357     const struct coresight_ops_sink *sink_ops;
0358     const struct coresight_ops_link *link_ops;
0359     const struct coresight_ops_source *source_ops;
0360     const struct coresight_ops_helper *helper_ops;
0361     const struct coresight_ops_ect *ect_ops;
0362 };
0363 
0364 #if IS_ENABLED(CONFIG_CORESIGHT)
0365 
0366 static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa,
0367                           u32 offset)
0368 {
0369     if (likely(csa->io_mem))
0370         return readl_relaxed(csa->base + offset);
0371 
0372     return csa->read(offset, true, false);
0373 }
0374 
0375 static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset)
0376 {
0377     if (likely(csa->io_mem))
0378         return readl(csa->base + offset);
0379 
0380     return csa->read(offset, false, false);
0381 }
0382 
0383 static inline void csdev_access_relaxed_write32(struct csdev_access *csa,
0384                         u32 val, u32 offset)
0385 {
0386     if (likely(csa->io_mem))
0387         writel_relaxed(val, csa->base + offset);
0388     else
0389         csa->write(val, offset, true, false);
0390 }
0391 
0392 static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset)
0393 {
0394     if (likely(csa->io_mem))
0395         writel(val, csa->base + offset);
0396     else
0397         csa->write(val, offset, false, false);
0398 }
0399 
0400 #ifdef CONFIG_64BIT
0401 
0402 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
0403                           u32 offset)
0404 {
0405     if (likely(csa->io_mem))
0406         return readq_relaxed(csa->base + offset);
0407 
0408     return csa->read(offset, true, true);
0409 }
0410 
0411 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
0412 {
0413     if (likely(csa->io_mem))
0414         return readq(csa->base + offset);
0415 
0416     return csa->read(offset, false, true);
0417 }
0418 
0419 static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
0420                         u64 val, u32 offset)
0421 {
0422     if (likely(csa->io_mem))
0423         writeq_relaxed(val, csa->base + offset);
0424     else
0425         csa->write(val, offset, true, true);
0426 }
0427 
0428 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
0429 {
0430     if (likely(csa->io_mem))
0431         writeq(val, csa->base + offset);
0432     else
0433         csa->write(val, offset, false, true);
0434 }
0435 
0436 #else   /* !CONFIG_64BIT */
0437 
0438 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
0439                           u32 offset)
0440 {
0441     WARN_ON(1);
0442     return 0;
0443 }
0444 
0445 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
0446 {
0447     WARN_ON(1);
0448     return 0;
0449 }
0450 
0451 static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
0452                         u64 val, u32 offset)
0453 {
0454     WARN_ON(1);
0455 }
0456 
0457 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
0458 {
0459     WARN_ON(1);
0460 }
0461 #endif  /* CONFIG_64BIT */
0462 
0463 static inline bool coresight_is_percpu_source(struct coresight_device *csdev)
0464 {
0465     return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) &&
0466            (csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC);
0467 }
0468 
0469 static inline bool coresight_is_percpu_sink(struct coresight_device *csdev)
0470 {
0471     return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) &&
0472            (csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM);
0473 }
0474 
0475 extern struct coresight_device *
0476 coresight_register(struct coresight_desc *desc);
0477 extern void coresight_unregister(struct coresight_device *csdev);
0478 extern int coresight_enable(struct coresight_device *csdev);
0479 extern void coresight_disable(struct coresight_device *csdev);
0480 extern int coresight_timeout(struct csdev_access *csa, u32 offset,
0481                  int position, int value);
0482 
0483 extern int coresight_claim_device(struct coresight_device *csdev);
0484 extern int coresight_claim_device_unlocked(struct coresight_device *csdev);
0485 
0486 extern void coresight_disclaim_device(struct coresight_device *csdev);
0487 extern void coresight_disclaim_device_unlocked(struct coresight_device *csdev);
0488 extern char *coresight_alloc_device_name(struct coresight_dev_list *devs,
0489                      struct device *dev);
0490 
0491 extern bool coresight_loses_context_with_cpu(struct device *dev);
0492 
0493 u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset);
0494 u32 coresight_read32(struct coresight_device *csdev, u32 offset);
0495 void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset);
0496 void coresight_relaxed_write32(struct coresight_device *csdev,
0497                    u32 val, u32 offset);
0498 u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset);
0499 u64 coresight_read64(struct coresight_device *csdev, u32 offset);
0500 void coresight_relaxed_write64(struct coresight_device *csdev,
0501                    u64 val, u32 offset);
0502 void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset);
0503 
0504 #else
0505 static inline struct coresight_device *
0506 coresight_register(struct coresight_desc *desc) { return NULL; }
0507 static inline void coresight_unregister(struct coresight_device *csdev) {}
0508 static inline int
0509 coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
0510 static inline void coresight_disable(struct coresight_device *csdev) {}
0511 
0512 static inline int coresight_timeout(struct csdev_access *csa, u32 offset,
0513                     int position, int value)
0514 {
0515     return 1;
0516 }
0517 
0518 static inline int coresight_claim_device_unlocked(struct coresight_device *csdev)
0519 {
0520     return -EINVAL;
0521 }
0522 
0523 static inline int coresight_claim_device(struct coresight_device *csdev)
0524 {
0525     return -EINVAL;
0526 }
0527 
0528 static inline void coresight_disclaim_device(struct coresight_device *csdev) {}
0529 static inline void coresight_disclaim_device_unlocked(struct coresight_device *csdev) {}
0530 
0531 static inline bool coresight_loses_context_with_cpu(struct device *dev)
0532 {
0533     return false;
0534 }
0535 
0536 static inline u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset)
0537 {
0538     WARN_ON_ONCE(1);
0539     return 0;
0540 }
0541 
0542 static inline u32 coresight_read32(struct coresight_device *csdev, u32 offset)
0543 {
0544     WARN_ON_ONCE(1);
0545     return 0;
0546 }
0547 
0548 static inline void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset)
0549 {
0550 }
0551 
0552 static inline void coresight_relaxed_write32(struct coresight_device *csdev,
0553                          u32 val, u32 offset)
0554 {
0555 }
0556 
0557 static inline u64 coresight_relaxed_read64(struct coresight_device *csdev,
0558                        u32 offset)
0559 {
0560     WARN_ON_ONCE(1);
0561     return 0;
0562 }
0563 
0564 static inline u64 coresight_read64(struct coresight_device *csdev, u32 offset)
0565 {
0566     WARN_ON_ONCE(1);
0567     return 0;
0568 }
0569 
0570 static inline void coresight_relaxed_write64(struct coresight_device *csdev,
0571                          u64 val, u32 offset)
0572 {
0573 }
0574 
0575 static inline void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset)
0576 {
0577 }
0578 
0579 #endif      /* IS_ENABLED(CONFIG_CORESIGHT) */
0580 
0581 extern int coresight_get_cpu(struct device *dev);
0582 
0583 struct coresight_platform_data *coresight_get_platform_data(struct device *dev);
0584 
0585 #endif      /* _LINUX_COREISGHT_H */
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