include/linux/coresight-pmu.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright(C) 2015 Linaro Limited. All rights reserved.
0004  * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
0005  */
0006
0007 #ifndef _LINUX_CORESIGHT_PMU_H
0008 #define _LINUX_CORESIGHT_PMU_H
0009
0010 #define CORESIGHT_ETM_PMU_NAME "cs_etm"
0011 #define CORESIGHT_ETM_PMU_SEED  0x10
0012
0013 /*
0014  * Below are the definition of bit offsets for perf option, and works as
0015  * arbitrary values for all ETM versions.
0016  *
0017  * Most of them are orignally from ETMv3.5/PTM's ETMCR config, therefore,
0018  * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and
0019  * directly use below macros as config bits.
0020  */
0021 #define ETM_OPT_BRANCH_BROADCAST 8
0022 #define ETM_OPT_CYCACC      12
0023 #define ETM_OPT_CTXTID      14
0024 #define ETM_OPT_CTXTID2     15
0025 #define ETM_OPT_TS      28
0026 #define ETM_OPT_RETSTK      29
0027
0028 /* ETMv4 CONFIGR programming bits for the ETM OPTs */
0029 #define ETM4_CFG_BIT_BB         3
0030 #define ETM4_CFG_BIT_CYCACC 4
0031 #define ETM4_CFG_BIT_CTXTID 6
0032 #define ETM4_CFG_BIT_VMID   7
0033 #define ETM4_CFG_BIT_TS     11
0034 #define ETM4_CFG_BIT_RETSTK 12
0035 #define ETM4_CFG_BIT_VMID_OPT   15
0036
0037 static inline int coresight_get_trace_id(int cpu)
0038 {
0039     /*
0040      * A trace ID of value 0 is invalid, so let's start at some
0041      * random value that fits in 7 bits and go from there.  Since
0042      * the common convention is to have data trace IDs be I(N) + 1,
0043      * set instruction trace IDs as a function of the CPU number.
0044      */
0045     return (CORESIGHT_ETM_PMU_SEED + (cpu * 2));
0046 }
0047
0048 #endif