linux/clk/ti.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * TI clock drivers support
0004  *
0005  * Copyright (C) 2013 Texas Instruments, Inc.
0006  */
0007 #ifndef __LINUX_CLK_TI_H__
0008 #define __LINUX_CLK_TI_H__
0009
0010 #include <linux/clk-provider.h>
0011 #include <linux/clkdev.h>
0012
0013 /**
0014  * struct clk_omap_reg - OMAP register declaration
0015  * @offset: offset from the master IP module base address
0016  * @index: index of the master IP module
0017  */
0018 struct clk_omap_reg {
0019     void __iomem *ptr;
0020     u16 offset;
0021     u8 index;
0022     u8 flags;
0023 };
0024
0025 /**
0026  * struct dpll_data - DPLL registers and integration data
0027  * @mult_div1_reg: register containing the DPLL M and N bitfields
0028  * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
0029  * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
0030  * @clk_bypass: struct clk_hw pointer to the clock's bypass clock input
0031  * @clk_ref: struct clk_hw pointer to the clock's reference clock input
0032  * @control_reg: register containing the DPLL mode bitfield
0033  * @enable_mask: mask of the DPLL mode bitfield in @control_reg
0034  * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
0035  * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
0036  * @last_rounded_m4xen: cache of the last M4X result of
0037  *          omap4_dpll_regm4xen_round_rate()
0038  * @last_rounded_lpmode: cache of the last lpmode result of
0039  *           omap4_dpll_lpmode_recalc()
0040  * @max_multiplier: maximum valid non-bypass multiplier value (actual)
0041  * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
0042  * @min_divider: minimum valid non-bypass divider value (actual)
0043  * @max_divider: maximum valid non-bypass divider value (actual)
0044  * @max_rate: maximum clock rate for the DPLL
0045  * @modes: possible values of @enable_mask
0046  * @autoidle_reg: register containing the DPLL autoidle mode bitfield
0047  * @idlest_reg: register containing the DPLL idle status bitfield
0048  * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
0049  * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
0050  * @dcc_mask: mask of the DPLL DCC correction bitfield @mult_div1_reg
0051  * @dcc_rate: rate atleast which DCC @dcc_mask must be set
0052  * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
0053  * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
0054  * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
0055  * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
0056  * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
0057  * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
0058  * @ssc_deltam_reg: register containing the DPLL SSC frequency spreading
0059  * @ssc_modfreq_reg: register containing the DPLL SSC modulation frequency
0060  * @ssc_modfreq_mant_mask: mask of the mantissa component in @ssc_modfreq_reg
0061  * @ssc_modfreq_exp_mask: mask of the exponent component in @ssc_modfreq_reg
0062  * @ssc_enable_mask: mask of the DPLL SSC enable bit in @control_reg
0063  * @ssc_downspread_mask: mask of the DPLL SSC low frequency only bit in
0064  *                       @control_reg
0065  * @ssc_modfreq: the DPLL SSC frequency modulation in kHz
0066  * @ssc_deltam: the DPLL SSC frequency spreading in permille (10th of percent)
0067  * @ssc_downspread: require the only low frequency spread of the DPLL in SSC
0068  *                   mode
0069  * @flags: DPLL type/features (see below)
0070  *
0071  * Possible values for @flags:
0072  * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
0073  *
0074  * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
0075  *
0076  * XXX Some DPLLs have multiple bypass inputs, so it's not technically
0077  * correct to only have one @clk_bypass pointer.
0078  *
0079  * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
0080  * @last_rounded_n) should be separated from the runtime-fixed fields
0081  * and placed into a different structure, so that the runtime-fixed data
0082  * can be placed into read-only space.
0083  */
0084 struct dpll_data {
0085     struct clk_omap_reg mult_div1_reg;
0086     u32         mult_mask;
0087     u32         div1_mask;
0088     struct clk_hw       *clk_bypass;
0089     struct clk_hw       *clk_ref;
0090     struct clk_omap_reg control_reg;
0091     u32         enable_mask;
0092     unsigned long       last_rounded_rate;
0093     u16         last_rounded_m;
0094     u8          last_rounded_m4xen;
0095     u8          last_rounded_lpmode;
0096     u16         max_multiplier;
0097     u8          last_rounded_n;
0098     u8          min_divider;
0099     u16         max_divider;
0100     unsigned long       max_rate;
0101     u8          modes;
0102     struct clk_omap_reg autoidle_reg;
0103     struct clk_omap_reg idlest_reg;
0104     u32         autoidle_mask;
0105     u32         freqsel_mask;
0106     u32         idlest_mask;
0107     u32         dco_mask;
0108     u32         sddiv_mask;
0109     u32         dcc_mask;
0110     unsigned long       dcc_rate;
0111     u32         lpmode_mask;
0112     u32         m4xen_mask;
0113     u8          auto_recal_bit;
0114     u8          recal_en_bit;
0115     u8          recal_st_bit;
0116     struct clk_omap_reg ssc_deltam_reg;
0117     struct clk_omap_reg ssc_modfreq_reg;
0118     u32         ssc_deltam_int_mask;
0119     u32         ssc_deltam_frac_mask;
0120     u32         ssc_modfreq_mant_mask;
0121     u32         ssc_modfreq_exp_mask;
0122     u32                     ssc_enable_mask;
0123     u32                     ssc_downspread_mask;
0124     u32                     ssc_modfreq;
0125     u32                     ssc_deltam;
0126     bool                    ssc_downspread;
0127     u8          flags;
0128 };
0129
0130 struct clk_hw_omap;
0131
0132 /**
0133  * struct clk_hw_omap_ops - OMAP clk ops
0134  * @find_idlest: find idlest register information for a clock
0135  * @find_companion: find companion clock register information for a clock,
0136  *          basically converts CM_ICLKEN* <-> CM_FCLKEN*
0137  * @allow_idle: enables autoidle hardware functionality for a clock
0138  * @deny_idle: prevent autoidle hardware functionality for a clock
0139  */
0140 struct clk_hw_omap_ops {
0141     void    (*find_idlest)(struct clk_hw_omap *oclk,
0142                    struct clk_omap_reg *idlest_reg,
0143                    u8 *idlest_bit, u8 *idlest_val);
0144     void    (*find_companion)(struct clk_hw_omap *oclk,
0145                   struct clk_omap_reg *other_reg,
0146                   u8 *other_bit);
0147     void    (*allow_idle)(struct clk_hw_omap *oclk);
0148     void    (*deny_idle)(struct clk_hw_omap *oclk);
0149 };
0150
0151 /**
0152  * struct clk_hw_omap - OMAP struct clk
0153  * @node: list_head connecting this clock into the full clock list
0154  * @enable_reg: register to write to enable the clock (see @enable_bit)
0155  * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
0156  * @flags: see "struct clk.flags possibilities" above
0157  * @clksel_reg: for clksel clks, register va containing src/divisor select
0158  * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
0159  * @clkdm_name: clockdomain name that this clock is contained in
0160  * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
0161  * @ops: clock ops for this clock
0162  */
0163 struct clk_hw_omap {
0164     struct clk_hw       hw;
0165     struct list_head    node;
0166     unsigned long       fixed_rate;
0167     u8          fixed_div;
0168     struct clk_omap_reg enable_reg;
0169     u8          enable_bit;
0170     unsigned long       flags;
0171     struct clk_omap_reg clksel_reg;
0172     struct dpll_data    *dpll_data;
0173     const char      *clkdm_name;
0174     struct clockdomain  *clkdm;
0175     const struct clk_hw_omap_ops    *ops;
0176     u32         context;
0177     int         autoidle_count;
0178 };
0179
0180 /*
0181  * struct clk_hw_omap.flags possibilities
0182  *
0183  * XXX document the rest of the clock flags here
0184  *
0185  * ENABLE_REG_32BIT: (OMAP1 only) clock control register must be accessed
0186  *     with 32bit ops, by default OMAP1 uses 16bit ops.
0187  * CLOCK_IDLE_CONTROL: (OMAP1 only) clock has autoidle support.
0188  * CLOCK_NO_IDLE_PARENT: (OMAP1 only) when clock is enabled, its parent
0189  *     clock is put to no-idle mode.
0190  * ENABLE_ON_INIT: Clock is enabled on init.
0191  * INVERT_ENABLE: By default, clock enable bit behavior is '1' enable, '0'
0192  *     disable. This inverts the behavior making '0' enable and '1' disable.
0193  * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
0194  *     bits share the same register.  This flag allows the
0195  *     omap4_dpllmx*() code to determine which GATE_CTRL bit field
0196  *     should be used.  This is a temporary solution - a better approach
0197  *     would be to associate clock type-specific data with the clock,
0198  *     similar to the struct dpll_data approach.
0199  */
0200 #define ENABLE_REG_32BIT    (1 << 0)    /* Use 32-bit access */
0201 #define CLOCK_IDLE_CONTROL  (1 << 1)
0202 #define CLOCK_NO_IDLE_PARENT    (1 << 2)
0203 #define ENABLE_ON_INIT      (1 << 3)    /* Enable upon framework init */
0204 #define INVERT_ENABLE       (1 << 4)    /* 0 enables, 1 disables */
0205 #define CLOCK_CLKOUTX2      (1 << 5)
0206
0207 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
0208 #define DPLL_LOW_POWER_STOP 0x1
0209 #define DPLL_LOW_POWER_BYPASS   0x5
0210 #define DPLL_LOCKED     0x7
0211
0212 /* DPLL Type and DCO Selection Flags */
0213 #define DPLL_J_TYPE     0x1
0214
0215 /* Static memmap indices */
0216 enum {
0217     TI_CLKM_CM = 0,
0218     TI_CLKM_CM2,
0219     TI_CLKM_PRM,
0220     TI_CLKM_SCRM,
0221     TI_CLKM_CTRL,
0222     TI_CLKM_CTRL_AUX,
0223     TI_CLKM_PLLSS,
0224     CLK_MAX_MEMMAPS
0225 };
0226
0227 /**
0228  * struct ti_clk_ll_ops - low-level ops for clocks
0229  * @clk_readl: pointer to register read function
0230  * @clk_writel: pointer to register write function
0231  * @clk_rmw: pointer to register read-modify-write function
0232  * @clkdm_clk_enable: pointer to clockdomain enable function
0233  * @clkdm_clk_disable: pointer to clockdomain disable function
0234  * @clkdm_lookup: pointer to clockdomain lookup function
0235  * @cm_wait_module_ready: pointer to CM module wait ready function
0236  * @cm_split_idlest_reg: pointer to CM module function to split idlest reg
0237  *
0238  * Low-level ops are generally used by the basic clock types (clk-gate,
0239  * clk-mux, clk-divider etc.) to provide support for various low-level
0240  * hadrware interfaces (direct MMIO, regmap etc.), and is initialized
0241  * by board code. Low-level ops also contain some other platform specific
0242  * operations not provided directly by clock drivers.
0243  */
0244 struct ti_clk_ll_ops {
0245     u32 (*clk_readl)(const struct clk_omap_reg *reg);
0246     void    (*clk_writel)(u32 val, const struct clk_omap_reg *reg);
0247     void    (*clk_rmw)(u32 val, u32 mask, const struct clk_omap_reg *reg);
0248     int (*clkdm_clk_enable)(struct clockdomain *clkdm, struct clk *clk);
0249     int (*clkdm_clk_disable)(struct clockdomain *clkdm,
0250                      struct clk *clk);
0251     struct clockdomain * (*clkdm_lookup)(const char *name);
0252     int (*cm_wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg,
0253                     u8 idlest_shift);
0254     int (*cm_split_idlest_reg)(struct clk_omap_reg *idlest_reg,
0255                        s16 *prcm_inst, u8 *idlest_reg_id);
0256 };
0257
0258 #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
0259
0260 bool omap2_clk_is_hw_omap(struct clk_hw *hw);
0261 int omap2_clk_disable_autoidle_all(void);
0262 int omap2_clk_enable_autoidle_all(void);
0263 int omap2_clk_allow_idle(struct clk *clk);
0264 int omap2_clk_deny_idle(struct clk *clk);
0265 unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
0266                     unsigned long parent_rate);
0267 int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate,
0268                  unsigned long parent_rate);
0269 void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
0270 void omap2xxx_clkt_vps_init(void);
0271 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
0272
0273 void ti_dt_clk_init_retry_clks(void);
0274 void ti_dt_clockdomains_setup(void);
0275 int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops);
0276
0277 struct regmap;
0278
0279 int omap2_clk_provider_init(struct device_node *parent, int index,
0280                 struct regmap *syscon, void __iomem *mem);
0281 void omap2_clk_legacy_provider_init(int index, void __iomem *mem);
0282
0283 int omap3430_dt_clk_init(void);
0284 int omap3630_dt_clk_init(void);
0285 int am35xx_dt_clk_init(void);
0286 int dm814x_dt_clk_init(void);
0287 int dm816x_dt_clk_init(void);
0288 int omap4xxx_dt_clk_init(void);
0289 int omap5xxx_dt_clk_init(void);
0290 int dra7xx_dt_clk_init(void);
0291 int am33xx_dt_clk_init(void);
0292 int am43xx_dt_clk_init(void);
0293 int omap2420_dt_clk_init(void);
0294 int omap2430_dt_clk_init(void);
0295
0296 struct ti_clk_features {
0297     u32 flags;
0298     long fint_min;
0299     long fint_max;
0300     long fint_band1_max;
0301     long fint_band2_min;
0302     u8 dpll_bypass_vals;
0303     u8 cm_idlest_val;
0304 };
0305
0306 #define TI_CLK_DPLL_HAS_FREQSEL         BIT(0)
0307 #define TI_CLK_DPLL4_DENY_REPROGRAM     BIT(1)
0308 #define TI_CLK_DISABLE_CLKDM_CONTROL        BIT(2)
0309 #define TI_CLK_ERRATA_I810          BIT(3)
0310 #define TI_CLK_CLKCTRL_COMPAT           BIT(4)
0311 #define TI_CLK_DEVICE_TYPE_GP           BIT(5)
0312
0313 void ti_clk_setup_features(struct ti_clk_features *features);
0314 const struct ti_clk_features *ti_clk_get_features(void);
0315 bool ti_clk_is_in_standby(struct clk *clk);
0316 int omap3_noncore_dpll_save_context(struct clk_hw *hw);
0317 void omap3_noncore_dpll_restore_context(struct clk_hw *hw);
0318
0319 int omap3_core_dpll_save_context(struct clk_hw *hw);
0320 void omap3_core_dpll_restore_context(struct clk_hw *hw);
0321
0322 extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
0323
0324 #ifdef CONFIG_ATAGS
0325 int omap3430_clk_legacy_init(void);
0326 int omap3430es1_clk_legacy_init(void);
0327 int omap36xx_clk_legacy_init(void);
0328 int am35xx_clk_legacy_init(void);
0329 #else
0330 static inline int omap3430_clk_legacy_init(void) { return -ENXIO; }
0331 static inline int omap3430es1_clk_legacy_init(void) { return -ENXIO; }
0332 static inline int omap36xx_clk_legacy_init(void) { return -ENXIO; }
0333 static inline int am35xx_clk_legacy_init(void) { return -ENXIO; }
0334 #endif
0335
0336
0337 #endif