linux/clk/tegra.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2012-2020, NVIDIA CORPORATION.  All rights reserved.
0004  */
0005
0006 #ifndef __LINUX_CLK_TEGRA_H_
0007 #define __LINUX_CLK_TEGRA_H_
0008
0009 #include <linux/types.h>
0010 #include <linux/bug.h>
0011
0012 /*
0013  * Tegra CPU clock and reset control ops
0014  *
0015  * wait_for_reset:
0016  *  keep waiting until the CPU in reset state
0017  * put_in_reset:
0018  *  put the CPU in reset state
0019  * out_of_reset:
0020  *  release the CPU from reset state
0021  * enable_clock:
0022  *  CPU clock un-gate
0023  * disable_clock:
0024  *  CPU clock gate
0025  * rail_off_ready:
0026  *  CPU is ready for rail off
0027  * suspend:
0028  *  save the clock settings when CPU go into low-power state
0029  * resume:
0030  *  restore the clock settings when CPU exit low-power state
0031  */
0032 struct tegra_cpu_car_ops {
0033     void (*wait_for_reset)(u32 cpu);
0034     void (*put_in_reset)(u32 cpu);
0035     void (*out_of_reset)(u32 cpu);
0036     void (*enable_clock)(u32 cpu);
0037     void (*disable_clock)(u32 cpu);
0038 #ifdef CONFIG_PM_SLEEP
0039     bool (*rail_off_ready)(void);
0040     void (*suspend)(void);
0041     void (*resume)(void);
0042 #endif
0043 };
0044
0045 #ifdef CONFIG_ARCH_TEGRA
0046 extern struct tegra_cpu_car_ops *tegra_cpu_car_ops;
0047
0048 static inline void tegra_wait_cpu_in_reset(u32 cpu)
0049 {
0050     if (WARN_ON(!tegra_cpu_car_ops->wait_for_reset))
0051         return;
0052
0053     tegra_cpu_car_ops->wait_for_reset(cpu);
0054 }
0055
0056 static inline void tegra_put_cpu_in_reset(u32 cpu)
0057 {
0058     if (WARN_ON(!tegra_cpu_car_ops->put_in_reset))
0059         return;
0060
0061     tegra_cpu_car_ops->put_in_reset(cpu);
0062 }
0063
0064 static inline void tegra_cpu_out_of_reset(u32 cpu)
0065 {
0066     if (WARN_ON(!tegra_cpu_car_ops->out_of_reset))
0067         return;
0068
0069     tegra_cpu_car_ops->out_of_reset(cpu);
0070 }
0071
0072 static inline void tegra_enable_cpu_clock(u32 cpu)
0073 {
0074     if (WARN_ON(!tegra_cpu_car_ops->enable_clock))
0075         return;
0076
0077     tegra_cpu_car_ops->enable_clock(cpu);
0078 }
0079
0080 static inline void tegra_disable_cpu_clock(u32 cpu)
0081 {
0082     if (WARN_ON(!tegra_cpu_car_ops->disable_clock))
0083         return;
0084
0085     tegra_cpu_car_ops->disable_clock(cpu);
0086 }
0087 #else
0088 static inline void tegra_wait_cpu_in_reset(u32 cpu)
0089 {
0090 }
0091
0092 static inline void tegra_put_cpu_in_reset(u32 cpu)
0093 {
0094 }
0095
0096 static inline void tegra_cpu_out_of_reset(u32 cpu)
0097 {
0098 }
0099
0100 static inline void tegra_enable_cpu_clock(u32 cpu)
0101 {
0102 }
0103
0104 static inline void tegra_disable_cpu_clock(u32 cpu)
0105 {
0106 }
0107 #endif
0108
0109 #if defined(CONFIG_ARCH_TEGRA) && defined(CONFIG_PM_SLEEP)
0110 static inline bool tegra_cpu_rail_off_ready(void)
0111 {
0112     if (WARN_ON(!tegra_cpu_car_ops->rail_off_ready))
0113         return false;
0114
0115     return tegra_cpu_car_ops->rail_off_ready();
0116 }
0117
0118 static inline void tegra_cpu_clock_suspend(void)
0119 {
0120     if (WARN_ON(!tegra_cpu_car_ops->suspend))
0121         return;
0122
0123     tegra_cpu_car_ops->suspend();
0124 }
0125
0126 static inline void tegra_cpu_clock_resume(void)
0127 {
0128     if (WARN_ON(!tegra_cpu_car_ops->resume))
0129         return;
0130
0131     tegra_cpu_car_ops->resume();
0132 }
0133 #else
0134 static inline bool tegra_cpu_rail_off_ready(void)
0135 {
0136     return false;
0137 }
0138
0139 static inline void tegra_cpu_clock_suspend(void)
0140 {
0141 }
0142
0143 static inline void tegra_cpu_clock_resume(void)
0144 {
0145 }
0146 #endif
0147
0148 struct clk;
0149 struct tegra_emc;
0150
0151 typedef long (tegra20_clk_emc_round_cb)(unsigned long rate,
0152                     unsigned long min_rate,
0153                     unsigned long max_rate,
0154                     void *arg);
0155 typedef int (tegra124_emc_prepare_timing_change_cb)(struct tegra_emc *emc,
0156                             unsigned long rate);
0157 typedef void (tegra124_emc_complete_timing_change_cb)(struct tegra_emc *emc,
0158                               unsigned long rate);
0159
0160 struct tegra210_clk_emc_config {
0161     unsigned long rate;
0162     bool same_freq;
0163     u32 value;
0164
0165     unsigned long parent_rate;
0166     u8 parent;
0167 };
0168
0169 struct tegra210_clk_emc_provider {
0170     struct module *owner;
0171     struct device *dev;
0172
0173     struct tegra210_clk_emc_config *configs;
0174     unsigned int num_configs;
0175
0176     int (*set_rate)(struct device *dev,
0177             const struct tegra210_clk_emc_config *config);
0178 };
0179
0180 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
0181 void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb,
0182                     void *cb_arg);
0183 int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same);
0184 #else
0185 static inline void
0186 tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb,
0187                    void *cb_arg)
0188 {
0189 }
0190
0191 static inline int
0192 tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same)
0193 {
0194     return 0;
0195 }
0196 #endif
0197
0198 #ifdef CONFIG_TEGRA124_CLK_EMC
0199 void tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb,
0200                     tegra124_emc_complete_timing_change_cb *complete_cb);
0201 #else
0202 static inline void
0203 tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb,
0204                    tegra124_emc_complete_timing_change_cb *complete_cb)
0205 {
0206 }
0207 #endif
0208
0209 #ifdef CONFIG_ARCH_TEGRA_210_SOC
0210 int tegra210_plle_hw_sequence_start(void);
0211 bool tegra210_plle_hw_sequence_is_enabled(void);
0212 void tegra210_xusb_pll_hw_control_enable(void);
0213 void tegra210_xusb_pll_hw_sequence_start(void);
0214 void tegra210_sata_pll_hw_control_enable(void);
0215 void tegra210_sata_pll_hw_sequence_start(void);
0216 void tegra210_set_sata_pll_seq_sw(bool state);
0217 void tegra210_put_utmipll_in_iddq(void);
0218 void tegra210_put_utmipll_out_iddq(void);
0219 int tegra210_clk_handle_mbist_war(unsigned int id);
0220 void tegra210_clk_emc_dll_enable(bool flag);
0221 void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value);
0222 void tegra210_clk_emc_update_setting(u32 emc_src_value);
0223
0224 int tegra210_clk_emc_attach(struct clk *clk,
0225                 struct tegra210_clk_emc_provider *provider);
0226 void tegra210_clk_emc_detach(struct clk *clk);
0227 #else
0228 static inline int tegra210_plle_hw_sequence_start(void)
0229 {
0230     return 0;
0231 }
0232
0233 static inline bool tegra210_plle_hw_sequence_is_enabled(void)
0234 {
0235     return false;
0236 }
0237
0238 static inline int tegra210_clk_handle_mbist_war(unsigned int id)
0239 {
0240     return 0;
0241 }
0242
0243 static inline int
0244 tegra210_clk_emc_attach(struct clk *clk,
0245             struct tegra210_clk_emc_provider *provider)
0246 {
0247     return 0;
0248 }
0249
0250 static inline void tegra210_xusb_pll_hw_control_enable(void) {}
0251 static inline void tegra210_xusb_pll_hw_sequence_start(void) {}
0252 static inline void tegra210_sata_pll_hw_control_enable(void) {}
0253 static inline void tegra210_sata_pll_hw_sequence_start(void) {}
0254 static inline void tegra210_set_sata_pll_seq_sw(bool state) {}
0255 static inline void tegra210_put_utmipll_in_iddq(void) {}
0256 static inline void tegra210_put_utmipll_out_iddq(void) {}
0257 static inline void tegra210_clk_emc_dll_enable(bool flag) {}
0258 static inline void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value) {}
0259 static inline void tegra210_clk_emc_update_setting(u32 emc_src_value) {}
0260 static inline void tegra210_clk_emc_detach(struct clk *clk) {}
0261 #endif
0262
0263 #endif /* __LINUX_CLK_TEGRA_H_ */