linux/clk/at91_pmc.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * include/linux/clk/at91_pmc.h
0004  *
0005  * Copyright (C) 2005 Ivan Kokshaysky
0006  * Copyright (C) SAN People
0007  *
0008  * Power Management Controller (PMC) - System peripherals registers.
0009  * Based on AT91RM9200 datasheet revision E.
0010  */
0011
0012 #ifndef AT91_PMC_H
0013 #define AT91_PMC_H
0014
0015 #define AT91_PMC_V1     (1)         /* PMC version 1 */
0016 #define AT91_PMC_V2     (2)         /* PMC version 2 [SAM9X60] */
0017
0018 #define AT91_PMC_SCER       0x00            /* System Clock Enable Register */
0019 #define AT91_PMC_SCDR       0x04            /* System Clock Disable Register */
0020
0021 #define AT91_PMC_SCSR       0x08            /* System Clock Status Register */
0022 #define     AT91_PMC_PCK        (1 <<  0)       /* Processor Clock */
0023 #define     AT91RM9200_PMC_UDP  (1 <<  1)       /* USB Devcice Port Clock [AT91RM9200 only] */
0024 #define     AT91RM9200_PMC_MCKUDP   (1 <<  2)       /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
0025 #define     AT91RM9200_PMC_UHP  (1 <<  4)       /* USB Host Port Clock [AT91RM9200 only] */
0026 #define     AT91SAM926x_PMC_UHP (1 <<  6)       /* USB Host Port Clock [AT91SAM926x only] */
0027 #define     AT91SAM926x_PMC_UDP (1 <<  7)       /* USB Devcice Port Clock [AT91SAM926x only] */
0028 #define     AT91_PMC_PCK0       (1 <<  8)       /* Programmable Clock 0 */
0029 #define     AT91_PMC_PCK1       (1 <<  9)       /* Programmable Clock 1 */
0030 #define     AT91_PMC_PCK2       (1 << 10)       /* Programmable Clock 2 */
0031 #define     AT91_PMC_PCK3       (1 << 11)       /* Programmable Clock 3 */
0032 #define     AT91_PMC_PCK4       (1 << 12)       /* Programmable Clock 4 [AT572D940HF only] */
0033 #define     AT91_PMC_HCK0       (1 << 16)       /* AHB Clock (USB host) [AT91SAM9261 only] */
0034 #define     AT91_PMC_HCK1       (1 << 17)       /* AHB Clock (LCD) [AT91SAM9261 only] */
0035
0036 #define AT91_PMC_PLL_CTRL0      0x0C        /* PLL Control Register 0 [for SAM9X60] */
0037 #define     AT91_PMC_PLL_CTRL0_ENPLL    (1 << 28)   /* Enable PLL */
0038 #define     AT91_PMC_PLL_CTRL0_ENPLLCK  (1 << 29)   /* Enable PLL clock for PMC */
0039 #define     AT91_PMC_PLL_CTRL0_ENLOCK   (1 << 31)   /* Enable PLL lock */
0040
0041 #define AT91_PMC_PLL_CTRL1      0x10        /* PLL Control Register 1 [for SAM9X60] */
0042
0043 #define AT91_PMC_PCER       0x10            /* Peripheral Clock Enable Register */
0044 #define AT91_PMC_PCDR       0x14            /* Peripheral Clock Disable Register */
0045 #define AT91_PMC_PCSR       0x18            /* Peripheral Clock Status Register */
0046
0047 #define AT91_PMC_PLL_ACR    0x18            /* PLL Analog Control Register [for SAM9X60] */
0048 #define     AT91_PMC_PLL_ACR_DEFAULT_UPLL   0x12020010UL    /* Default PLL ACR value for UPLL */
0049 #define     AT91_PMC_PLL_ACR_DEFAULT_PLLA   0x00020010UL    /* Default PLL ACR value for PLLA */
0050 #define     AT91_PMC_PLL_ACR_UTMIVR     (1 << 12)   /* UPLL Voltage regulator Control */
0051 #define     AT91_PMC_PLL_ACR_UTMIBG     (1 << 13)   /* UPLL Bandgap Control */
0052
0053 #define AT91_CKGR_UCKR      0x1C            /* UTMI Clock Register [some SAM9] */
0054 #define     AT91_PMC_UPLLEN     (1   << 16)     /* UTMI PLL Enable */
0055 #define     AT91_PMC_UPLLCOUNT  (0xf << 20)     /* UTMI PLL Start-up Time */
0056 #define     AT91_PMC_BIASEN     (1   << 24)     /* UTMI BIAS Enable */
0057 #define     AT91_PMC_BIASCOUNT  (0xf << 28)     /* UTMI BIAS Start-up Time */
0058
0059 #define AT91_PMC_PLL_UPDT       0x1C        /* PMC PLL update register [for SAM9X60] */
0060 #define     AT91_PMC_PLL_UPDT_UPDATE    (1 << 8)    /* Update PLL settings */
0061 #define     AT91_PMC_PLL_UPDT_ID        (1 << 0)    /* PLL ID */
0062 #define     AT91_PMC_PLL_UPDT_ID_MSK    (0xf)       /* PLL ID mask */
0063 #define     AT91_PMC_PLL_UPDT_STUPTIM   (0xff << 16)    /* Startup time */
0064
0065 #define AT91_CKGR_MOR       0x20            /* Main Oscillator Register [not on SAM9RL] */
0066 #define     AT91_PMC_MOSCEN     (1    <<  0)        /* Main Oscillator Enable */
0067 #define     AT91_PMC_OSCBYPASS  (1    <<  1)        /* Oscillator Bypass */
0068 #define     AT91_PMC_WAITMODE   (1    <<  2)        /* Wait Mode Command */
0069 #define     AT91_PMC_MOSCRCEN   (1    <<  3)        /* Main On-Chip RC Oscillator Enable [some SAM9] */
0070 #define     AT91_PMC_OSCOUNT    (0xff <<  8)        /* Main Oscillator Start-up Time */
0071 #define     AT91_PMC_KEY_MASK   (0xff << 16)
0072 #define     AT91_PMC_KEY        (0x37 << 16)        /* MOR Writing Key */
0073 #define     AT91_PMC_MOSCSEL    (1    << 24)        /* Main Oscillator Selection [some SAM9] */
0074 #define     AT91_PMC_CFDEN      (1    << 25)        /* Clock Failure Detector Enable [some SAM9] */
0075
0076 #define AT91_CKGR_MCFR      0x24            /* Main Clock Frequency Register */
0077 #define     AT91_PMC_MAINF      (0xffff <<  0)      /* Main Clock Frequency */
0078 #define     AT91_PMC_MAINRDY    (1  << 16)      /* Main Clock Ready */
0079
0080 #define AT91_CKGR_PLLAR     0x28            /* PLL A Register */
0081
0082 #define AT91_PMC_RATIO      0x2c            /* Processor clock ratio register [SAMA7G5 only] */
0083 #define     AT91_PMC_RATIO_RATIO    (0xf)       /* CPU clock ratio. */
0084
0085 #define AT91_CKGR_PLLBR     0x2c            /* PLL B Register */
0086 #define     AT91_PMC_DIV        (0xff  <<  0)       /* Divider */
0087 #define     AT91_PMC_PLLCOUNT   (0x3f  <<  8)       /* PLL Counter */
0088 #define     AT91_PMC_OUT        (3     << 14)       /* PLL Clock Frequency Range */
0089 #define     AT91_PMC_MUL        (0x7ff << 16)       /* PLL Multiplier */
0090 #define     AT91_PMC_MUL_GET(n) ((n) >> 16 & 0x7ff)
0091 #define     AT91_PMC3_MUL       (0x7f  << 18)       /* PLL Multiplier [SAMA5 only] */
0092 #define     AT91_PMC3_MUL_GET(n)    ((n) >> 18 & 0x7f)
0093 #define     AT91_PMC_USBDIV     (3     << 28)       /* USB Divisor (PLLB only) */
0094 #define         AT91_PMC_USBDIV_1       (0 << 28)
0095 #define         AT91_PMC_USBDIV_2       (1 << 28)
0096 #define         AT91_PMC_USBDIV_4       (2 << 28)
0097 #define     AT91_PMC_USB96M     (1     << 28)       /* Divider by 2 Enable (PLLB only) */
0098
0099 #define AT91_PMC_CPU_CKR    0x28            /* CPU Clock Register */
0100
0101 #define AT91_PMC_MCKR       0x30            /* Master Clock Register */
0102 #define     AT91_PMC_CSS        (3 <<  0)       /* Master Clock Selection */
0103 #define         AT91_PMC_CSS_SLOW       (0 << 0)
0104 #define         AT91_PMC_CSS_MAIN       (1 << 0)
0105 #define         AT91_PMC_CSS_PLLA       (2 << 0)
0106 #define         AT91_PMC_CSS_PLLB       (3 << 0)
0107 #define         AT91_PMC_CSS_UPLL       (3 << 0)    /* [some SAM9 only] */
0108 #define     PMC_PRES_OFFSET     2
0109 #define     AT91_PMC_PRES       (7 <<  PMC_PRES_OFFSET)     /* Master Clock Prescaler */
0110 #define         AT91_PMC_PRES_1         (0 << PMC_PRES_OFFSET)
0111 #define         AT91_PMC_PRES_2         (1 << PMC_PRES_OFFSET)
0112 #define         AT91_PMC_PRES_4         (2 << PMC_PRES_OFFSET)
0113 #define         AT91_PMC_PRES_8         (3 << PMC_PRES_OFFSET)
0114 #define         AT91_PMC_PRES_16        (4 << PMC_PRES_OFFSET)
0115 #define         AT91_PMC_PRES_32        (5 << PMC_PRES_OFFSET)
0116 #define         AT91_PMC_PRES_64        (6 << PMC_PRES_OFFSET)
0117 #define     PMC_ALT_PRES_OFFSET 4
0118 #define     AT91_PMC_ALT_PRES   (7 <<  PMC_ALT_PRES_OFFSET)     /* Master Clock Prescaler [alternate location] */
0119 #define         AT91_PMC_ALT_PRES_1     (0 << PMC_ALT_PRES_OFFSET)
0120 #define         AT91_PMC_ALT_PRES_2     (1 << PMC_ALT_PRES_OFFSET)
0121 #define         AT91_PMC_ALT_PRES_4     (2 << PMC_ALT_PRES_OFFSET)
0122 #define         AT91_PMC_ALT_PRES_8     (3 << PMC_ALT_PRES_OFFSET)
0123 #define         AT91_PMC_ALT_PRES_16        (4 << PMC_ALT_PRES_OFFSET)
0124 #define         AT91_PMC_ALT_PRES_32        (5 << PMC_ALT_PRES_OFFSET)
0125 #define         AT91_PMC_ALT_PRES_64        (6 << PMC_ALT_PRES_OFFSET)
0126 #define     AT91_PMC_MDIV       (3 <<  8)       /* Master Clock Division */
0127 #define         AT91RM9200_PMC_MDIV_1       (0 << 8)    /* [AT91RM9200 only] */
0128 #define         AT91RM9200_PMC_MDIV_2       (1 << 8)
0129 #define         AT91RM9200_PMC_MDIV_3       (2 << 8)
0130 #define         AT91RM9200_PMC_MDIV_4       (3 << 8)
0131 #define         AT91SAM9_PMC_MDIV_1     (0 << 8)    /* [SAM9 only] */
0132 #define         AT91SAM9_PMC_MDIV_2     (1 << 8)
0133 #define         AT91SAM9_PMC_MDIV_4     (2 << 8)
0134 #define         AT91SAM9_PMC_MDIV_6     (3 << 8)    /* [some SAM9 only] */
0135 #define         AT91SAM9_PMC_MDIV_3     (3 << 8)    /* [some SAM9 only] */
0136 #define     AT91_PMC_PDIV       (1 << 12)       /* Processor Clock Division [some SAM9 only] */
0137 #define         AT91_PMC_PDIV_1         (0 << 12)
0138 #define         AT91_PMC_PDIV_2         (1 << 12)
0139 #define     AT91_PMC_PLLADIV2   (1 << 12)       /* PLLA divisor by 2 [some SAM9 only] */
0140 #define         AT91_PMC_PLLADIV2_OFF       (0 << 12)
0141 #define         AT91_PMC_PLLADIV2_ON        (1 << 12)
0142 #define     AT91_PMC_H32MXDIV   BIT(24)
0143
0144 #define AT91_PMC_MCR_V2     0x30                /* Master Clock Register [SAMA7G5 only] */
0145 #define     AT91_PMC_MCR_V2_ID_MSK  (0xF)
0146 #define         AT91_PMC_MCR_V2_ID(_id)     ((_id) & AT91_PMC_MCR_V2_ID_MSK)
0147 #define     AT91_PMC_MCR_V2_CMD (1 << 7)
0148 #define     AT91_PMC_MCR_V2_DIV (7 << 8)
0149 #define         AT91_PMC_MCR_V2_DIV1        (0 << 8)
0150 #define         AT91_PMC_MCR_V2_DIV2        (1 << 8)
0151 #define         AT91_PMC_MCR_V2_DIV4        (2 << 8)
0152 #define         AT91_PMC_MCR_V2_DIV8        (3 << 8)
0153 #define         AT91_PMC_MCR_V2_DIV16       (4 << 8)
0154 #define         AT91_PMC_MCR_V2_DIV32       (5 << 8)
0155 #define         AT91_PMC_MCR_V2_DIV64       (6 << 8)
0156 #define         AT91_PMC_MCR_V2_DIV3        (7 << 8)
0157 #define     AT91_PMC_MCR_V2_CSS (0x1F << 16)
0158 #define         AT91_PMC_MCR_V2_CSS_MD_SLCK (0 << 16)
0159 #define         AT91_PMC_MCR_V2_CSS_TD_SLCK (1 << 16)
0160 #define         AT91_PMC_MCR_V2_CSS_MAINCK  (2 << 16)
0161 #define         AT91_PMC_MCR_V2_CSS_MCK0    (3 << 16)
0162 #define         AT91_PMC_MCR_V2_CSS_SYSPLL  (5 << 16)
0163 #define         AT91_PMC_MCR_V2_CSS_DDRPLL  (6 << 16)
0164 #define         AT91_PMC_MCR_V2_CSS_IMGPLL  (7 << 16)
0165 #define         AT91_PMC_MCR_V2_CSS_BAUDPLL (8 << 16)
0166 #define         AT91_PMC_MCR_V2_CSS_AUDIOPLL    (9 << 16)
0167 #define         AT91_PMC_MCR_V2_CSS_ETHPLL  (10 << 16)
0168 #define     AT91_PMC_MCR_V2_EN  (1 << 28)
0169
0170 #define AT91_PMC_XTALF      0x34            /* Main XTAL Frequency Register [SAMA7G5 only] */
0171
0172 #define AT91_PMC_USB        0x38            /* USB Clock Register [some SAM9 only] */
0173 #define     AT91_PMC_USBS       (0x1 <<  0)     /* USB OHCI Input clock selection */
0174 #define         AT91_PMC_USBS_PLLA      (0 << 0)
0175 #define         AT91_PMC_USBS_UPLL      (1 << 0)
0176 #define         AT91_PMC_USBS_PLLB      (1 << 0)    /* [AT91SAMN12 only] */
0177 #define     AT91_PMC_OHCIUSBDIV (0xF <<  8)     /* Divider for USB OHCI Clock */
0178 #define         AT91_PMC_OHCIUSBDIV_1   (0x0 <<  8)
0179 #define         AT91_PMC_OHCIUSBDIV_2   (0x1 <<  8)
0180
0181 #define AT91_PMC_SMD        0x3c            /* Soft Modem Clock Register [some SAM9 only] */
0182 #define     AT91_PMC_SMDS       (0x1  <<  0)        /* SMD input clock selection */
0183 #define     AT91_PMC_SMD_DIV    (0x1f <<  8)        /* SMD input clock divider */
0184 #define     AT91_PMC_SMDDIV(n)  (((n) <<  8) & AT91_PMC_SMD_DIV)
0185
0186 #define AT91_PMC_PCKR(n)    (0x40 + ((n) * 4))  /* Programmable Clock 0-N Registers */
0187 #define     AT91_PMC_ALT_PCKR_CSS   (0x7 <<  0)     /* Programmable Clock Source Selection [alternate length] */
0188 #define         AT91_PMC_CSS_MASTER     (4 << 0)    /* [some SAM9 only] */
0189 #define     AT91_PMC_CSSMCK     (0x1 <<  8)     /* CSS or Master Clock Selection */
0190 #define         AT91_PMC_CSSMCK_CSS     (0 << 8)
0191 #define         AT91_PMC_CSSMCK_MCK     (1 << 8)
0192
0193 #define AT91_PMC_IER        0x60            /* Interrupt Enable Register */
0194 #define AT91_PMC_IDR        0x64            /* Interrupt Disable Register */
0195 #define AT91_PMC_SR     0x68            /* Status Register */
0196 #define     AT91_PMC_MOSCS      (1 <<  0)       /* MOSCS Flag */
0197 #define     AT91_PMC_LOCKA      (1 <<  1)       /* PLLA Lock */
0198 #define     AT91_PMC_LOCKB      (1 <<  2)       /* PLLB Lock */
0199 #define     AT91_PMC_MCKRDY     (1 <<  3)       /* Master Clock */
0200 #define     AT91_PMC_LOCKU      (1 <<  6)       /* UPLL Lock [some SAM9] */
0201 #define     AT91_PMC_OSCSEL     (1 <<  7)       /* Slow Oscillator Selection [some SAM9] */
0202 #define     AT91_PMC_PCK0RDY    (1 <<  8)       /* Programmable Clock 0 */
0203 #define     AT91_PMC_PCK1RDY    (1 <<  9)       /* Programmable Clock 1 */
0204 #define     AT91_PMC_PCK2RDY    (1 << 10)       /* Programmable Clock 2 */
0205 #define     AT91_PMC_PCK3RDY    (1 << 11)       /* Programmable Clock 3 */
0206 #define     AT91_PMC_MOSCSELS   (1 << 16)       /* Main Oscillator Selection [some SAM9] */
0207 #define     AT91_PMC_MOSCRCS    (1 << 17)       /* Main On-Chip RC [some SAM9] */
0208 #define     AT91_PMC_CFDEV      (1 << 18)       /* Clock Failure Detector Event [some SAM9] */
0209 #define     AT91_PMC_GCKRDY     (1 << 24)       /* Generated Clocks */
0210 #define     AT91_PMC_MCKXRDY    (1 << 26)       /* Master Clock x [x=1..4] Ready Status */
0211 #define AT91_PMC_IMR        0x6c            /* Interrupt Mask Register */
0212
0213 #define AT91_PMC_FSMR       0x70        /* Fast Startup Mode Register */
0214 #define AT91_PMC_FSTT(n)    BIT(n)
0215 #define AT91_PMC_RTTAL      BIT(16)
0216 #define AT91_PMC_RTCAL      BIT(17)     /* RTC Alarm Enable */
0217 #define AT91_PMC_USBAL      BIT(18)     /* USB Resume Enable */
0218 #define AT91_PMC_SDMMC_CD   BIT(19)     /* SDMMC Card Detect Enable */
0219 #define AT91_PMC_LPM        BIT(20)     /* Low-power Mode */
0220 #define AT91_PMC_RXLP_MCE   BIT(24)     /* Backup UART Receive Enable */
0221 #define AT91_PMC_ACC_CE     BIT(25)     /* ACC Enable */
0222
0223 #define AT91_PMC_FSPR       0x74        /* Fast Startup Polarity Reg */
0224
0225 #define AT91_PMC_FS_INPUT_MASK  0x7ff
0226
0227 #define AT91_PMC_PLLICPR    0x80            /* PLL Charge Pump Current Register */
0228
0229 #define AT91_PMC_PROT       0xe4            /* Write Protect Mode Register [some SAM9] */
0230 #define     AT91_PMC_WPEN       (0x1  <<  0)        /* Write Protect Enable */
0231 #define     AT91_PMC_WPKEY      (0xffffff << 8)     /* Write Protect Key */
0232 #define     AT91_PMC_PROTKEY    (0x504d43 << 8)     /* Activation Code */
0233
0234 #define AT91_PMC_WPSR       0xe8            /* Write Protect Status Register [some SAM9] */
0235 #define     AT91_PMC_WPVS       (0x1  <<  0)        /* Write Protect Violation Status */
0236 #define     AT91_PMC_WPVSRC     (0xffff  <<  8)     /* Write Protect Violation Source */
0237
0238 #define AT91_PMC_PLL_ISR0   0xEC            /* PLL Interrupt Status Register 0 [SAM9X60 only] */
0239
0240 #define AT91_PMC_PCER1      0x100           /* Peripheral Clock Enable Register 1 [SAMA5 only]*/
0241 #define AT91_PMC_PCDR1      0x104           /* Peripheral Clock Enable Register 1 */
0242 #define AT91_PMC_PCSR1      0x108           /* Peripheral Clock Enable Register 1 */
0243
0244 #define AT91_PMC_PCR        0x10c           /* Peripheral Control Register [some SAM9 and SAMA5] */
0245 #define     AT91_PMC_PCR_PID_MASK       0x3f
0246 #define     AT91_PMC_PCR_CMD        (0x1  <<  12)               /* Command (read=0, write=1) */
0247 #define     AT91_PMC_PCR_GCKDIV_MASK    GENMASK(27, 20)
0248 #define     AT91_PMC_PCR_EN         (0x1  <<  28)               /* Enable */
0249 #define     AT91_PMC_PCR_GCKEN      (0x1  <<  29)               /* GCK Enable */
0250
0251 #define AT91_PMC_AUDIO_PLL0 0x14c
0252 #define     AT91_PMC_AUDIO_PLL_PLLEN    (1  <<  0)
0253 #define     AT91_PMC_AUDIO_PLL_PADEN    (1  <<  1)
0254 #define     AT91_PMC_AUDIO_PLL_PMCEN    (1  <<  2)
0255 #define     AT91_PMC_AUDIO_PLL_RESETN   (1  <<  3)
0256 #define     AT91_PMC_AUDIO_PLL_ND_OFFSET    8
0257 #define     AT91_PMC_AUDIO_PLL_ND_MASK  (0x7f << AT91_PMC_AUDIO_PLL_ND_OFFSET)
0258 #define     AT91_PMC_AUDIO_PLL_ND(n)    ((n)  << AT91_PMC_AUDIO_PLL_ND_OFFSET)
0259 #define     AT91_PMC_AUDIO_PLL_QDPMC_OFFSET 16
0260 #define     AT91_PMC_AUDIO_PLL_QDPMC_MASK   (0x7f << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET)
0261 #define     AT91_PMC_AUDIO_PLL_QDPMC(n) ((n)  << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET)
0262
0263 #define AT91_PMC_AUDIO_PLL1 0x150
0264 #define     AT91_PMC_AUDIO_PLL_FRACR_MASK       0x3fffff
0265 #define     AT91_PMC_AUDIO_PLL_QDPAD_OFFSET     24
0266 #define     AT91_PMC_AUDIO_PLL_QDPAD_MASK       (0x7f << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET)
0267 #define     AT91_PMC_AUDIO_PLL_QDPAD(n)     ((n)  << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET)
0268 #define     AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET AT91_PMC_AUDIO_PLL_QDPAD_OFFSET
0269 #define     AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK   (0x3  << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET)
0270 #define     AT91_PMC_AUDIO_PLL_QDPAD_DIV(n)     ((n)  << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET)
0271 #define     AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET  26
0272 #define     AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX 0x1f
0273 #define     AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK    (AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET)
0274 #define     AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(n)  ((n)  << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET)
0275
0276 #endif