can/platform/sja1000.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _CAN_PLATFORM_SJA1000_H
0003 #define _CAN_PLATFORM_SJA1000_H
0004
0005 /* clock divider register */
0006 #define CDR_CLKOUT_MASK 0x07
0007 #define CDR_CLK_OFF 0x08 /* Clock off (CLKOUT pin) */
0008 #define CDR_RXINPEN 0x20 /* TX1 output is RX irq output */
0009 #define CDR_CBP     0x40 /* CAN input comparator bypass */
0010 #define CDR_PELICAN 0x80 /* PeliCAN mode */
0011
0012 /* output control register */
0013 #define OCR_MODE_BIPHASE  0x00
0014 #define OCR_MODE_TEST     0x01
0015 #define OCR_MODE_NORMAL   0x02
0016 #define OCR_MODE_CLOCK    0x03
0017 #define OCR_MODE_MASK     0x07
0018 #define OCR_TX0_INVERT    0x04
0019 #define OCR_TX0_PULLDOWN  0x08
0020 #define OCR_TX0_PULLUP    0x10
0021 #define OCR_TX0_PUSHPULL  0x18
0022 #define OCR_TX1_INVERT    0x20
0023 #define OCR_TX1_PULLDOWN  0x40
0024 #define OCR_TX1_PULLUP    0x80
0025 #define OCR_TX1_PUSHPULL  0xc0
0026 #define OCR_TX_MASK       0xfc
0027 #define OCR_TX_SHIFT      2
0028
0029 struct sja1000_platform_data {
0030     u32 osc_freq;   /* CAN bus oscillator frequency in Hz */
0031
0032     u8 ocr;     /* output control register */
0033     u8 cdr;     /* clock divider register */
0034 };
0035
0036 #endif  /* !_CAN_PLATFORM_SJA1000_H */