linux/bcma/bcma_driver_pci.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef LINUX_BCMA_DRIVER_PCI_H_
0003 #define LINUX_BCMA_DRIVER_PCI_H_
0004
0005 #include <linux/types.h>
0006
0007 struct pci_dev;
0008
0009 /** PCI core registers. **/
0010 #define BCMA_CORE_PCI_CTL           0x0000  /* PCI Control */
0011 #define  BCMA_CORE_PCI_CTL_RST_OE       0x00000001 /* PCI_RESET Output Enable */
0012 #define  BCMA_CORE_PCI_CTL_RST          0x00000002 /* PCI_RESET driven out to pin */
0013 #define  BCMA_CORE_PCI_CTL_CLK_OE       0x00000004 /* Clock gate Output Enable */
0014 #define  BCMA_CORE_PCI_CTL_CLK          0x00000008 /* Gate for clock driven out to pin */
0015 #define BCMA_CORE_PCI_ARBCTL            0x0010  /* PCI Arbiter Control */
0016 #define  BCMA_CORE_PCI_ARBCTL_INTERN        0x00000001 /* Use internal arbiter */
0017 #define  BCMA_CORE_PCI_ARBCTL_EXTERN        0x00000002 /* Use external arbiter */
0018 #define  BCMA_CORE_PCI_ARBCTL_PARKID        0x00000006 /* Mask, selects which agent is parked on an idle bus */
0019 #define   BCMA_CORE_PCI_ARBCTL_PARKID_LAST  0x00000000 /* Last requestor */
0020 #define   BCMA_CORE_PCI_ARBCTL_PARKID_4710  0x00000002 /* 4710 */
0021 #define   BCMA_CORE_PCI_ARBCTL_PARKID_EXT0  0x00000004 /* External requestor 0 */
0022 #define   BCMA_CORE_PCI_ARBCTL_PARKID_EXT1  0x00000006 /* External requestor 1 */
0023 #define BCMA_CORE_PCI_ISTAT         0x0020  /* Interrupt status */
0024 #define  BCMA_CORE_PCI_ISTAT_INTA       0x00000001 /* PCI INTA# */
0025 #define  BCMA_CORE_PCI_ISTAT_INTB       0x00000002 /* PCI INTB# */
0026 #define  BCMA_CORE_PCI_ISTAT_SERR       0x00000004 /* PCI SERR# (write to clear) */
0027 #define  BCMA_CORE_PCI_ISTAT_PERR       0x00000008 /* PCI PERR# (write to clear) */
0028 #define  BCMA_CORE_PCI_ISTAT_PME        0x00000010 /* PCI PME# */
0029 #define BCMA_CORE_PCI_IMASK         0x0024  /* Interrupt mask */
0030 #define  BCMA_CORE_PCI_IMASK_INTA       0x00000001 /* PCI INTA# */
0031 #define  BCMA_CORE_PCI_IMASK_INTB       0x00000002 /* PCI INTB# */
0032 #define  BCMA_CORE_PCI_IMASK_SERR       0x00000004 /* PCI SERR# */
0033 #define  BCMA_CORE_PCI_IMASK_PERR       0x00000008 /* PCI PERR# */
0034 #define  BCMA_CORE_PCI_IMASK_PME        0x00000010 /* PCI PME# */
0035 #define BCMA_CORE_PCI_MBOX          0x0028  /* Backplane to PCI Mailbox */
0036 #define  BCMA_CORE_PCI_MBOX_F0_0        0x00000100 /* PCI function 0, INT 0 */
0037 #define  BCMA_CORE_PCI_MBOX_F0_1        0x00000200 /* PCI function 0, INT 1 */
0038 #define  BCMA_CORE_PCI_MBOX_F1_0        0x00000400 /* PCI function 1, INT 0 */
0039 #define  BCMA_CORE_PCI_MBOX_F1_1        0x00000800 /* PCI function 1, INT 1 */
0040 #define  BCMA_CORE_PCI_MBOX_F2_0        0x00001000 /* PCI function 2, INT 0 */
0041 #define  BCMA_CORE_PCI_MBOX_F2_1        0x00002000 /* PCI function 2, INT 1 */
0042 #define  BCMA_CORE_PCI_MBOX_F3_0        0x00004000 /* PCI function 3, INT 0 */
0043 #define  BCMA_CORE_PCI_MBOX_F3_1        0x00008000 /* PCI function 3, INT 1 */
0044 #define BCMA_CORE_PCI_BCAST_ADDR        0x0050  /* Backplane Broadcast Address */
0045 #define  BCMA_CORE_PCI_BCAST_ADDR_MASK      0x000000FF
0046 #define BCMA_CORE_PCI_BCAST_DATA        0x0054  /* Backplane Broadcast Data */
0047 #define BCMA_CORE_PCI_GPIO_IN           0x0060  /* rev >= 2 only */
0048 #define BCMA_CORE_PCI_GPIO_OUT          0x0064  /* rev >= 2 only */
0049 #define BCMA_CORE_PCI_GPIO_ENABLE       0x0068  /* rev >= 2 only */
0050 #define BCMA_CORE_PCI_GPIO_CTL          0x006C  /* rev >= 2 only */
0051 #define BCMA_CORE_PCI_SBTOPCI0          0x0100  /* Backplane to PCI translation 0 (sbtopci0) */
0052 #define  BCMA_CORE_PCI_SBTOPCI0_MASK        0xFC000000
0053 #define BCMA_CORE_PCI_SBTOPCI1          0x0104  /* Backplane to PCI translation 1 (sbtopci1) */
0054 #define  BCMA_CORE_PCI_SBTOPCI1_MASK        0xFC000000
0055 #define BCMA_CORE_PCI_SBTOPCI2          0x0108  /* Backplane to PCI translation 2 (sbtopci2) */
0056 #define  BCMA_CORE_PCI_SBTOPCI2_MASK        0xC0000000
0057 #define BCMA_CORE_PCI_CONFIG_ADDR       0x0120  /* pcie config space access */
0058 #define BCMA_CORE_PCI_CONFIG_DATA       0x0124  /* pcie config space access */
0059 #define BCMA_CORE_PCI_MDIO_CONTROL      0x0128  /* controls the mdio access */
0060 #define  BCMA_CORE_PCI_MDIOCTL_DIVISOR_MASK 0x7f    /* clock to be used on MDIO */
0061 #define  BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL  0x2
0062 #define  BCMA_CORE_PCI_MDIOCTL_PREAM_EN     0x80    /* Enable preamble sequnce */
0063 #define  BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE  0x100   /* Tranaction complete */
0064 #define BCMA_CORE_PCI_MDIO_DATA         0x012c  /* Data to the mdio access */
0065 #define  BCMA_CORE_PCI_MDIODATA_MASK        0x0000ffff /* data 2 bytes */
0066 #define  BCMA_CORE_PCI_MDIODATA_TA      0x00020000 /* Turnaround */
0067 #define  BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD 18  /* Regaddr shift (rev < 10) */
0068 #define  BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD    0x003c0000 /* Regaddr Mask (rev < 10) */
0069 #define  BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD 22  /* Physmedia devaddr shift (rev < 10) */
0070 #define  BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD    0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */
0071 #define  BCMA_CORE_PCI_MDIODATA_REGADDR_SHF 18  /* Regaddr shift */
0072 #define  BCMA_CORE_PCI_MDIODATA_REGADDR_MASK    0x007c0000 /* Regaddr Mask */
0073 #define  BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF 23  /* Physmedia devaddr shift */
0074 #define  BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK    0x0f800000 /* Physmedia devaddr Mask */
0075 #define  BCMA_CORE_PCI_MDIODATA_WRITE       0x10000000 /* write Transaction */
0076 #define  BCMA_CORE_PCI_MDIODATA_READ        0x20000000 /* Read Transaction */
0077 #define  BCMA_CORE_PCI_MDIODATA_START       0x40000000 /* start of Transaction */
0078 #define  BCMA_CORE_PCI_MDIODATA_DEV_ADDR    0x0 /* dev address for serdes */
0079 #define  BCMA_CORE_PCI_MDIODATA_BLK_ADDR    0x1F    /* blk address for serdes */
0080 #define  BCMA_CORE_PCI_MDIODATA_DEV_PLL     0x1d    /* SERDES PLL Dev */
0081 #define  BCMA_CORE_PCI_MDIODATA_DEV_TX      0x1e    /* SERDES TX Dev */
0082 #define  BCMA_CORE_PCI_MDIODATA_DEV_RX      0x1f    /* SERDES RX Dev */
0083 #define BCMA_CORE_PCI_PCIEIND_ADDR      0x0130  /* indirect access to the internal register */
0084 #define BCMA_CORE_PCI_PCIEIND_DATA      0x0134  /* Data to/from the internal register */
0085 #define BCMA_CORE_PCI_CLKREQENCTRL      0x0138  /*  >= rev 6, Clkreq rdma control */
0086 #define BCMA_CORE_PCI_PCICFG0           0x0400  /* PCI config space 0 (rev >= 8) */
0087 #define BCMA_CORE_PCI_PCICFG1           0x0500  /* PCI config space 1 (rev >= 8) */
0088 #define BCMA_CORE_PCI_PCICFG2           0x0600  /* PCI config space 2 (rev >= 8) */
0089 #define BCMA_CORE_PCI_PCICFG3           0x0700  /* PCI config space 3 (rev >= 8) */
0090 #define BCMA_CORE_PCI_SPROM(wordoffset)     (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
0091 #define  BCMA_CORE_PCI_SPROM_PI_OFFSET      0   /* first word */
0092 #define   BCMA_CORE_PCI_SPROM_PI_MASK       0xf000  /* bit 15:12 */
0093 #define   BCMA_CORE_PCI_SPROM_PI_SHIFT      12  /* bit 15:12 */
0094 #define  BCMA_CORE_PCI_SPROM_MISC_CONFIG    5   /* word 5 */
0095 #define   BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST 0x8000  /* bit 15 */
0096 #define   BCMA_CORE_PCI_SPROM_CLKREQ_OFFSET_REV5    20  /* word 20 for srom rev <= 5 */
0097 #define   BCMA_CORE_PCI_SPROM_CLKREQ_ENB    0x0800  /* bit 11 */
0098
0099 /* SBtoPCIx */
0100 #define BCMA_CORE_PCI_SBTOPCI_MEM       0x00000000
0101 #define BCMA_CORE_PCI_SBTOPCI_IO        0x00000001
0102 #define BCMA_CORE_PCI_SBTOPCI_CFG0      0x00000002
0103 #define BCMA_CORE_PCI_SBTOPCI_CFG1      0x00000003
0104 #define BCMA_CORE_PCI_SBTOPCI_PREF      0x00000004 /* Prefetch enable */
0105 #define BCMA_CORE_PCI_SBTOPCI_BURST     0x00000008 /* Burst enable */
0106 #define BCMA_CORE_PCI_SBTOPCI_MRM       0x00000020 /* Memory Read Multiple */
0107 #define BCMA_CORE_PCI_SBTOPCI_RC        0x00000030 /* Read Command mask (rev >= 11) */
0108 #define  BCMA_CORE_PCI_SBTOPCI_RC_READ      0x00000000 /* Memory read */
0109 #define  BCMA_CORE_PCI_SBTOPCI_RC_READL     0x00000010 /* Memory read line */
0110 #define  BCMA_CORE_PCI_SBTOPCI_RC_READM     0x00000020 /* Memory read multiple */
0111
0112 /* PCIE protocol PHY diagnostic registers */
0113 #define BCMA_CORE_PCI_PLP_MODEREG       0x200   /* Mode */
0114 #define BCMA_CORE_PCI_PLP_STATUSREG     0x204   /* Status */
0115 #define  BCMA_CORE_PCI_PLP_POLARITYINV_STAT 0x10    /* Status reg PCIE_PLP_STATUSREG */
0116 #define BCMA_CORE_PCI_PLP_LTSSMCTRLREG      0x208   /* LTSSM control */
0117 #define BCMA_CORE_PCI_PLP_LTLINKNUMREG      0x20c   /* Link Training Link number */
0118 #define BCMA_CORE_PCI_PLP_LTLANENUMREG      0x210   /* Link Training Lane number */
0119 #define BCMA_CORE_PCI_PLP_LTNFTSREG     0x214   /* Link Training N_FTS */
0120 #define BCMA_CORE_PCI_PLP_ATTNREG       0x218   /* Attention */
0121 #define BCMA_CORE_PCI_PLP_ATTNMASKREG       0x21C   /* Attention Mask */
0122 #define BCMA_CORE_PCI_PLP_RXERRCTR      0x220   /* Rx Error */
0123 #define BCMA_CORE_PCI_PLP_RXFRMERRCTR       0x224   /* Rx Framing Error */
0124 #define BCMA_CORE_PCI_PLP_RXERRTHRESHREG    0x228   /* Rx Error threshold */
0125 #define BCMA_CORE_PCI_PLP_TESTCTRLREG       0x22C   /* Test Control reg */
0126 #define BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG 0x230   /* SERDES Control Override */
0127 #define BCMA_CORE_PCI_PLP_TIMINGOVRDREG     0x234   /* Timing param override */
0128 #define BCMA_CORE_PCI_PLP_RXTXSMDIAGREG     0x238   /* RXTX State Machine Diag */
0129 #define BCMA_CORE_PCI_PLP_LTSSMDIAGREG      0x23C   /* LTSSM State Machine Diag */
0130
0131 /* PCIE protocol DLLP diagnostic registers */
0132 #define BCMA_CORE_PCI_DLLP_LCREG        0x100   /* Link Control */
0133 #define BCMA_CORE_PCI_DLLP_LSREG        0x104   /* Link Status */
0134 #define BCMA_CORE_PCI_DLLP_LAREG        0x108   /* Link Attention */
0135 #define  BCMA_CORE_PCI_DLLP_LSREG_LINKUP    (1 << 16)
0136 #define BCMA_CORE_PCI_DLLP_LAMASKREG        0x10C   /* Link Attention Mask */
0137 #define BCMA_CORE_PCI_DLLP_NEXTTXSEQNUMREG  0x110   /* Next Tx Seq Num */
0138 #define BCMA_CORE_PCI_DLLP_ACKEDTXSEQNUMREG 0x114   /* Acked Tx Seq Num */
0139 #define BCMA_CORE_PCI_DLLP_PURGEDTXSEQNUMREG    0x118   /* Purged Tx Seq Num */
0140 #define BCMA_CORE_PCI_DLLP_RXSEQNUMREG      0x11C   /* Rx Sequence Number */
0141 #define BCMA_CORE_PCI_DLLP_LRREG        0x120   /* Link Replay */
0142 #define BCMA_CORE_PCI_DLLP_LACKTOREG        0x124   /* Link Ack Timeout */
0143 #define BCMA_CORE_PCI_DLLP_PMTHRESHREG      0x128   /* Power Management Threshold */
0144 #define  BCMA_CORE_PCI_ASPMTIMER_EXTEND     0x01000000 /* > rev7: enable extend ASPM timer */
0145 #define BCMA_CORE_PCI_DLLP_RTRYWPREG        0x12C   /* Retry buffer write ptr */
0146 #define BCMA_CORE_PCI_DLLP_RTRYRPREG        0x130   /* Retry buffer Read ptr */
0147 #define BCMA_CORE_PCI_DLLP_RTRYPPREG        0x134   /* Retry buffer Purged ptr */
0148 #define BCMA_CORE_PCI_DLLP_RTRRWREG     0x138   /* Retry buffer Read/Write */
0149 #define BCMA_CORE_PCI_DLLP_ECTHRESHREG      0x13C   /* Error Count Threshold */
0150 #define BCMA_CORE_PCI_DLLP_TLPERRCTRREG     0x140   /* TLP Error Counter */
0151 #define BCMA_CORE_PCI_DLLP_ERRCTRREG        0x144   /* Error Counter */
0152 #define BCMA_CORE_PCI_DLLP_NAKRXCTRREG      0x148   /* NAK Received Counter */
0153 #define BCMA_CORE_PCI_DLLP_TESTREG      0x14C   /* Test */
0154 #define BCMA_CORE_PCI_DLLP_PKTBIST      0x150   /* Packet BIST */
0155 #define BCMA_CORE_PCI_DLLP_PCIE11       0x154   /* DLLP PCIE 1.1 reg */
0156
0157 /* SERDES RX registers */
0158 #define BCMA_CORE_PCI_SERDES_RX_CTRL        1   /* Rx cntrl */
0159 #define  BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE 0x80    /* rxpolarity_force */
0160 #define  BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY  0x40    /* rxpolarity_value */
0161 #define BCMA_CORE_PCI_SERDES_RX_TIMER1      2   /* Rx Timer1 */
0162 #define BCMA_CORE_PCI_SERDES_RX_CDR     6   /* CDR */
0163 #define BCMA_CORE_PCI_SERDES_RX_CDRBW       7   /* CDR BW */
0164
0165 /* SERDES PLL registers */
0166 #define BCMA_CORE_PCI_SERDES_PLL_CTRL       1   /* PLL control reg */
0167 #define BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN   0x4000  /* bit 14 is FREQDET on */
0168
0169 /* PCIcore specific boardflags */
0170 #define BCMA_CORE_PCI_BFL_NOPCI         0x00000400 /* Board leaves PCI floating */
0171
0172 /* PCIE Config space accessing MACROS */
0173 #define BCMA_CORE_PCI_CFG_BUS_SHIFT     24  /* Bus shift */
0174 #define BCMA_CORE_PCI_CFG_SLOT_SHIFT        19  /* Slot/Device shift */
0175 #define BCMA_CORE_PCI_CFG_FUN_SHIFT     16  /* Function shift */
0176 #define BCMA_CORE_PCI_CFG_OFF_SHIFT     0   /* Register shift */
0177
0178 #define BCMA_CORE_PCI_CFG_BUS_MASK      0xff    /* Bus mask */
0179 #define BCMA_CORE_PCI_CFG_SLOT_MASK     0x1f    /* Slot/Device mask */
0180 #define BCMA_CORE_PCI_CFG_FUN_MASK      7   /* Function mask */
0181 #define BCMA_CORE_PCI_CFG_OFF_MASK      0xfff   /* Register mask */
0182
0183 #define BCMA_CORE_PCI_CFG_DEVCTRL       0xd8
0184
0185 #define BCMA_CORE_PCI_
0186
0187 /* MDIO devices (SERDES modules) */
0188 #define BCMA_CORE_PCI_MDIO_IEEE0        0x000
0189 #define BCMA_CORE_PCI_MDIO_IEEE1        0x001
0190 #define BCMA_CORE_PCI_MDIO_BLK0         0x800
0191 #define BCMA_CORE_PCI_MDIO_BLK1         0x801
0192 #define  BCMA_CORE_PCI_MDIO_BLK1_MGMT0      0x16
0193 #define  BCMA_CORE_PCI_MDIO_BLK1_MGMT1      0x17
0194 #define  BCMA_CORE_PCI_MDIO_BLK1_MGMT2      0x18
0195 #define  BCMA_CORE_PCI_MDIO_BLK1_MGMT3      0x19
0196 #define  BCMA_CORE_PCI_MDIO_BLK1_MGMT4      0x1A
0197 #define BCMA_CORE_PCI_MDIO_BLK2         0x802
0198 #define BCMA_CORE_PCI_MDIO_BLK3         0x803
0199 #define BCMA_CORE_PCI_MDIO_BLK4         0x804
0200 #define BCMA_CORE_PCI_MDIO_TXPLL        0x808   /* TXPLL register block idx */
0201 #define BCMA_CORE_PCI_MDIO_TXCTRL0      0x820
0202 #define BCMA_CORE_PCI_MDIO_SERDESID     0x831
0203 #define BCMA_CORE_PCI_MDIO_RXCTRL0      0x840
0204
0205 /* PCIE Root Capability Register bits (Host mode only) */
0206 #define BCMA_CORE_PCI_RC_CRS_VISIBILITY     0x0001
0207
0208 struct bcma_drv_pci;
0209 struct bcma_bus;
0210
0211 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
0212 struct bcma_drv_pci_host {
0213     struct bcma_drv_pci *pdev;
0214
0215     u32 host_cfg_addr;
0216     spinlock_t cfgspace_lock;
0217
0218     struct pci_controller pci_controller;
0219     struct pci_ops pci_ops;
0220     struct resource mem_resource;
0221     struct resource io_resource;
0222 };
0223 #endif
0224
0225 struct bcma_drv_pci {
0226     struct bcma_device *core;
0227     u8 early_setup_done:1;
0228     u8 setup_done:1;
0229     u8 hostmode:1;
0230
0231 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
0232     struct bcma_drv_pci_host *host_controller;
0233 #endif
0234 };
0235
0236 /* Register access */
0237 #define pcicore_read16(pc, offset)      bcma_read16((pc)->core, offset)
0238 #define pcicore_read32(pc, offset)      bcma_read32((pc)->core, offset)
0239 #define pcicore_write16(pc, offset, val)    bcma_write16((pc)->core, offset, val)
0240 #define pcicore_write32(pc, offset, val)    bcma_write32((pc)->core, offset, val)
0241
0242 #ifdef CONFIG_BCMA_DRIVER_PCI
0243 extern void bcma_core_pci_power_save(struct bcma_bus *bus, bool up);
0244 #else
0245 static inline void bcma_core_pci_power_save(struct bcma_bus *bus, bool up)
0246 {
0247 }
0248 #endif
0249
0250 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
0251 extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
0252 extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
0253 #else
0254 static inline int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev)
0255 {
0256     return -ENOTSUPP;
0257 }
0258 static inline int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
0259 {
0260     return -ENOTSUPP;
0261 }
0262 #endif
0263
0264 #endif /* LINUX_BCMA_DRIVER_PCI_H_ */