include/linux/arm-cci.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * CCI cache coherent interconnect support
0004  *
0005  * Copyright (C) 2013 ARM Ltd.
0006  */
0007
0008 #ifndef __LINUX_ARM_CCI_H
0009 #define __LINUX_ARM_CCI_H
0010
0011 #include <linux/errno.h>
0012 #include <linux/types.h>
0013
0014 #include <asm/arm-cci.h>
0015
0016 struct device_node;
0017
0018 #ifdef CONFIG_ARM_CCI
0019 extern bool cci_probed(void);
0020 #else
0021 static inline bool cci_probed(void) { return false; }
0022 #endif
0023
0024 #ifdef CONFIG_ARM_CCI400_PORT_CTRL
0025 extern int cci_ace_get_port(struct device_node *dn);
0026 extern int cci_disable_port_by_cpu(u64 mpidr);
0027 extern int __cci_control_port_by_device(struct device_node *dn, bool enable);
0028 extern int __cci_control_port_by_index(u32 port, bool enable);
0029 #else
0030 static inline int cci_ace_get_port(struct device_node *dn)
0031 {
0032     return -ENODEV;
0033 }
0034 static inline int cci_disable_port_by_cpu(u64 mpidr) { return -ENODEV; }
0035 static inline int __cci_control_port_by_device(struct device_node *dn,
0036                            bool enable)
0037 {
0038     return -ENODEV;
0039 }
0040 static inline int __cci_control_port_by_index(u32 port, bool enable)
0041 {
0042     return -ENODEV;
0043 }
0044 #endif
0045
0046 #define cci_disable_port_by_device(dev) \
0047     __cci_control_port_by_device(dev, false)
0048 #define cci_enable_port_by_device(dev) \
0049     __cci_control_port_by_device(dev, true)
0050 #define cci_disable_port_by_index(dev) \
0051     __cci_control_port_by_index(dev, false)
0052 #define cci_enable_port_by_index(dev) \
0053     __cci_control_port_by_index(dev, true)
0054
0055 #endif