include/linux/amd-iommu.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
0004  * Author: Joerg Roedel <joerg.roedel@amd.com>
0005  *         Leo Duran <leo.duran@amd.com>
0006  */
0007
0008 #ifndef _ASM_X86_AMD_IOMMU_H
0009 #define _ASM_X86_AMD_IOMMU_H
0010
0011 #include <linux/types.h>
0012
0013 struct amd_iommu;
0014
0015 /*
0016  * This is mainly used to communicate information back-and-forth
0017  * between SVM and IOMMU for setting up and tearing down posted
0018  * interrupt
0019  */
0020 struct amd_iommu_pi_data {
0021     u32 ga_tag;
0022     u32 prev_ga_tag;
0023     u64 base;
0024     bool is_guest_mode;
0025     struct vcpu_data *vcpu_data;
0026     void *ir_data;
0027 };
0028
0029 #ifdef CONFIG_AMD_IOMMU
0030
0031 struct task_struct;
0032 struct pci_dev;
0033
0034 extern int amd_iommu_detect(void);
0035 extern int amd_iommu_init_hardware(void);
0036
0037 /**
0038  * amd_iommu_init_device() - Init device for use with IOMMUv2 driver
0039  * @pdev: The PCI device to initialize
0040  * @pasids: Number of PASIDs to support for this device
0041  *
0042  * This function does all setup for the device pdev so that it can be
0043  * used with IOMMUv2.
0044  * Returns 0 on success or negative value on error.
0045  */
0046 extern int amd_iommu_init_device(struct pci_dev *pdev, int pasids);
0047
0048 /**
0049  * amd_iommu_free_device() - Free all IOMMUv2 related device resources
0050  *               and disable IOMMUv2 usage for this device
0051  * @pdev: The PCI device to disable IOMMUv2 usage for'
0052  */
0053 extern void amd_iommu_free_device(struct pci_dev *pdev);
0054
0055 /**
0056  * amd_iommu_bind_pasid() - Bind a given task to a PASID on a device
0057  * @pdev: The PCI device to bind the task to
0058  * @pasid: The PASID on the device the task should be bound to
0059  * @task: the task to bind
0060  *
0061  * The function returns 0 on success or a negative value on error.
0062  */
0063 extern int amd_iommu_bind_pasid(struct pci_dev *pdev, u32 pasid,
0064                 struct task_struct *task);
0065
0066 /**
0067  * amd_iommu_unbind_pasid() - Unbind a PASID from its task on
0068  *                a device
0069  * @pdev: The device of the PASID
0070  * @pasid: The PASID to unbind
0071  *
0072  * When this function returns the device is no longer using the PASID
0073  * and the PASID is no longer bound to its task.
0074  */
0075 extern void amd_iommu_unbind_pasid(struct pci_dev *pdev, u32 pasid);
0076
0077 /**
0078  * amd_iommu_set_invalid_ppr_cb() - Register a call-back for failed
0079  *                  PRI requests
0080  * @pdev: The PCI device the call-back should be registered for
0081  * @cb: The call-back function
0082  *
0083  * The IOMMUv2 driver invokes this call-back when it is unable to
0084  * successfully handle a PRI request. The device driver can then decide
0085  * which PRI response the device should see. Possible return values for
0086  * the call-back are:
0087  *
0088  * - AMD_IOMMU_INV_PRI_RSP_SUCCESS - Send SUCCESS back to the device
0089  * - AMD_IOMMU_INV_PRI_RSP_INVALID - Send INVALID back to the device
0090  * - AMD_IOMMU_INV_PRI_RSP_FAIL    - Send Failure back to the device,
0091  *                   the device is required to disable
0092  *                   PRI when it receives this response
0093  *
0094  * The function returns 0 on success or negative value on error.
0095  */
0096 #define AMD_IOMMU_INV_PRI_RSP_SUCCESS   0
0097 #define AMD_IOMMU_INV_PRI_RSP_INVALID   1
0098 #define AMD_IOMMU_INV_PRI_RSP_FAIL  2
0099
0100 typedef int (*amd_iommu_invalid_ppr_cb)(struct pci_dev *pdev,
0101                     u32 pasid,
0102                     unsigned long address,
0103                     u16);
0104
0105 extern int amd_iommu_set_invalid_ppr_cb(struct pci_dev *pdev,
0106                     amd_iommu_invalid_ppr_cb cb);
0107
0108 #define PPR_FAULT_EXEC  (1 << 1)
0109 #define PPR_FAULT_READ  (1 << 2)
0110 #define PPR_FAULT_WRITE (1 << 5)
0111 #define PPR_FAULT_USER  (1 << 6)
0112 #define PPR_FAULT_RSVD  (1 << 7)
0113 #define PPR_FAULT_GN    (1 << 8)
0114
0115 /**
0116  * amd_iommu_device_info() - Get information about IOMMUv2 support of a
0117  *               PCI device
0118  * @pdev: PCI device to query information from
0119  * @info: A pointer to an amd_iommu_device_info structure which will contain
0120  *    the information about the PCI device
0121  *
0122  * Returns 0 on success, negative value on error
0123  */
0124
0125 #define AMD_IOMMU_DEVICE_FLAG_ATS_SUP     0x1    /* ATS feature supported */
0126 #define AMD_IOMMU_DEVICE_FLAG_PRI_SUP     0x2    /* PRI feature supported */
0127 #define AMD_IOMMU_DEVICE_FLAG_PASID_SUP   0x4    /* PASID context supported */
0128 #define AMD_IOMMU_DEVICE_FLAG_EXEC_SUP    0x8    /* Device may request execution
0129                             on memory pages */
0130 #define AMD_IOMMU_DEVICE_FLAG_PRIV_SUP   0x10    /* Device may request
0131                             super-user privileges */
0132
0133 struct amd_iommu_device_info {
0134     int max_pasids;
0135     u32 flags;
0136 };
0137
0138 extern int amd_iommu_device_info(struct pci_dev *pdev,
0139                  struct amd_iommu_device_info *info);
0140
0141 /**
0142  * amd_iommu_set_invalidate_ctx_cb() - Register a call-back for invalidating
0143  *                     a pasid context. This call-back is
0144  *                     invoked when the IOMMUv2 driver needs to
0145  *                     invalidate a PASID context, for example
0146  *                     because the task that is bound to that
0147  *                     context is about to exit.
0148  *
0149  * @pdev: The PCI device the call-back should be registered for
0150  * @cb: The call-back function
0151  */
0152
0153 typedef void (*amd_iommu_invalidate_ctx)(struct pci_dev *pdev, u32 pasid);
0154
0155 extern int amd_iommu_set_invalidate_ctx_cb(struct pci_dev *pdev,
0156                        amd_iommu_invalidate_ctx cb);
0157 #else /* CONFIG_AMD_IOMMU */
0158
0159 static inline int amd_iommu_detect(void) { return -ENODEV; }
0160
0161 #endif /* CONFIG_AMD_IOMMU */
0162
0163 #if defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP)
0164
0165 /* IOMMU AVIC Function */
0166 extern int amd_iommu_register_ga_log_notifier(int (*notifier)(u32));
0167
0168 extern int
0169 amd_iommu_update_ga(int cpu, bool is_run, void *data);
0170
0171 extern int amd_iommu_activate_guest_mode(void *data);
0172 extern int amd_iommu_deactivate_guest_mode(void *data);
0173
0174 #else /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */
0175
0176 static inline int
0177 amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
0178 {
0179     return 0;
0180 }
0181
0182 static inline int
0183 amd_iommu_update_ga(int cpu, bool is_run, void *data)
0184 {
0185     return 0;
0186 }
0187
0188 static inline int amd_iommu_activate_guest_mode(void *data)
0189 {
0190     return 0;
0191 }
0192
0193 static inline int amd_iommu_deactivate_guest_mode(void *data)
0194 {
0195     return 0;
0196 }
0197 #endif /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */
0198
0199 int amd_iommu_get_num_iommus(void);
0200 bool amd_iommu_pc_supported(void);
0201 u8 amd_iommu_pc_get_max_banks(unsigned int idx);
0202 u8 amd_iommu_pc_get_max_counters(unsigned int idx);
0203 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn,
0204         u64 *value);
0205 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn,
0206         u64 *value);
0207 struct amd_iommu *get_amd_iommu(unsigned int idx);
0208
0209 #ifdef CONFIG_AMD_MEM_ENCRYPT
0210 int amd_iommu_snp_enable(void);
0211 #endif
0212
0213 #endif /* _ASM_X86_AMD_IOMMU_H */