linux/amba/serial.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *  linux/include/asm-arm/hardware/serial_amba.h
0004  *
0005  *  Internal header file for AMBA serial ports
0006  *
0007  *  Copyright (C) ARM Limited
0008  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
0009  */
0010 #ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_H
0011 #define ASM_ARM_HARDWARE_SERIAL_AMBA_H
0012
0013 #include <linux/types.h>
0014
0015 /* -------------------------------------------------------------------------------
0016  *  From AMBA UART (PL010) Block Specification
0017  * -------------------------------------------------------------------------------
0018  *  UART Register Offsets.
0019  */
0020 #define UART01x_DR      0x00    /* Data read or written from the interface. */
0021 #define UART01x_RSR     0x04    /* Receive status register (Read). */
0022 #define UART01x_ECR     0x04    /* Error clear register (Write). */
0023 #define UART010_LCRH        0x08    /* Line control register, high byte. */
0024 #define ST_UART011_DMAWM    0x08    /* DMA watermark configure register. */
0025 #define UART010_LCRM        0x0C    /* Line control register, middle byte. */
0026 #define ST_UART011_TIMEOUT  0x0C    /* Timeout period register. */
0027 #define UART010_LCRL        0x10    /* Line control register, low byte. */
0028 #define UART010_CR      0x14    /* Control register. */
0029 #define UART01x_FR      0x18    /* Flag register (Read only). */
0030 #define UART010_IIR     0x1C    /* Interrupt identification register (Read). */
0031 #define UART010_ICR     0x1C    /* Interrupt clear register (Write). */
0032 #define ST_UART011_LCRH_RX  0x1C    /* Rx line control register. */
0033 #define UART01x_ILPR        0x20    /* IrDA low power counter register. */
0034 #define UART011_IBRD        0x24    /* Integer baud rate divisor register. */
0035 #define UART011_FBRD        0x28    /* Fractional baud rate divisor register. */
0036 #define UART011_LCRH        0x2c    /* Line control register. */
0037 #define ST_UART011_LCRH_TX  0x2c    /* Tx Line control register. */
0038 #define UART011_CR      0x30    /* Control register. */
0039 #define UART011_IFLS        0x34    /* Interrupt fifo level select. */
0040 #define UART011_IMSC        0x38    /* Interrupt mask. */
0041 #define UART011_RIS     0x3c    /* Raw interrupt status. */
0042 #define UART011_MIS     0x40    /* Masked interrupt status. */
0043 #define UART011_ICR     0x44    /* Interrupt clear register. */
0044 #define UART011_DMACR       0x48    /* DMA control register. */
0045 #define ST_UART011_XFCR     0x50    /* XON/XOFF control register. */
0046 #define ST_UART011_XON1     0x54    /* XON1 register. */
0047 #define ST_UART011_XON2     0x58    /* XON2 register. */
0048 #define ST_UART011_XOFF1    0x5C    /* XON1 register. */
0049 #define ST_UART011_XOFF2    0x60    /* XON2 register. */
0050 #define ST_UART011_ITCR     0x80    /* Integration test control register. */
0051 #define ST_UART011_ITIP     0x84    /* Integration test input register. */
0052 #define ST_UART011_ABCR     0x100   /* Autobaud control register. */
0053 #define ST_UART011_ABIMSC   0x15C   /* Autobaud interrupt mask/clear register. */
0054
0055 /*
0056  * ZTE UART register offsets.  This UART has a radically different address
0057  * allocation from the ARM and ST variants, so we list all registers here.
0058  * We assume unlisted registers do not exist.
0059  */
0060 #define ZX_UART011_DR       0x04
0061 #define ZX_UART011_FR       0x14
0062 #define ZX_UART011_IBRD     0x24
0063 #define ZX_UART011_FBRD     0x28
0064 #define ZX_UART011_LCRH     0x30
0065 #define ZX_UART011_CR       0x34
0066 #define ZX_UART011_IFLS     0x38
0067 #define ZX_UART011_IMSC     0x40
0068 #define ZX_UART011_RIS      0x44
0069 #define ZX_UART011_MIS      0x48
0070 #define ZX_UART011_ICR      0x4c
0071 #define ZX_UART011_DMACR    0x50
0072
0073 #define UART011_DR_OE       (1 << 11)
0074 #define UART011_DR_BE       (1 << 10)
0075 #define UART011_DR_PE       (1 << 9)
0076 #define UART011_DR_FE       (1 << 8)
0077
0078 #define UART01x_RSR_OE      0x08
0079 #define UART01x_RSR_BE      0x04
0080 #define UART01x_RSR_PE      0x02
0081 #define UART01x_RSR_FE      0x01
0082
0083 #define UART011_FR_RI       0x100
0084 #define UART011_FR_TXFE     0x080
0085 #define UART011_FR_RXFF     0x040
0086 #define UART01x_FR_TXFF     0x020
0087 #define UART01x_FR_RXFE     0x010
0088 #define UART01x_FR_BUSY     0x008
0089 #define UART01x_FR_DCD      0x004
0090 #define UART01x_FR_DSR      0x002
0091 #define UART01x_FR_CTS      0x001
0092 #define UART01x_FR_TMSK     (UART01x_FR_TXFF + UART01x_FR_BUSY)
0093
0094 /*
0095  * Some bits of Flag Register on ZTE device have different position from
0096  * standard ones.
0097  */
0098 #define ZX_UART01x_FR_BUSY  0x100
0099 #define ZX_UART01x_FR_DSR   0x008
0100 #define ZX_UART01x_FR_CTS   0x002
0101 #define ZX_UART011_FR_RI    0x001
0102
0103 #define UART011_CR_CTSEN    0x8000  /* CTS hardware flow control */
0104 #define UART011_CR_RTSEN    0x4000  /* RTS hardware flow control */
0105 #define UART011_CR_OUT2     0x2000  /* OUT2 */
0106 #define UART011_CR_OUT1     0x1000  /* OUT1 */
0107 #define UART011_CR_RTS      0x0800  /* RTS */
0108 #define UART011_CR_DTR      0x0400  /* DTR */
0109 #define UART011_CR_RXE      0x0200  /* receive enable */
0110 #define UART011_CR_TXE      0x0100  /* transmit enable */
0111 #define UART011_CR_LBE      0x0080  /* loopback enable */
0112 #define UART010_CR_RTIE     0x0040
0113 #define UART010_CR_TIE      0x0020
0114 #define UART010_CR_RIE      0x0010
0115 #define UART010_CR_MSIE     0x0008
0116 #define ST_UART011_CR_OVSFACT   0x0008  /* Oversampling factor */
0117 #define UART01x_CR_IIRLP    0x0004  /* SIR low power mode */
0118 #define UART01x_CR_SIREN    0x0002  /* SIR enable */
0119 #define UART01x_CR_UARTEN   0x0001  /* UART enable */
0120
0121 #define UART011_LCRH_SPS    0x80
0122 #define UART01x_LCRH_WLEN_8 0x60
0123 #define UART01x_LCRH_WLEN_7 0x40
0124 #define UART01x_LCRH_WLEN_6 0x20
0125 #define UART01x_LCRH_WLEN_5 0x00
0126 #define UART01x_LCRH_FEN    0x10
0127 #define UART01x_LCRH_STP2   0x08
0128 #define UART01x_LCRH_EPS    0x04
0129 #define UART01x_LCRH_PEN    0x02
0130 #define UART01x_LCRH_BRK    0x01
0131
0132 #define ST_UART011_DMAWM_RX_1   (0 << 3)
0133 #define ST_UART011_DMAWM_RX_2   (1 << 3)
0134 #define ST_UART011_DMAWM_RX_4   (2 << 3)
0135 #define ST_UART011_DMAWM_RX_8   (3 << 3)
0136 #define ST_UART011_DMAWM_RX_16  (4 << 3)
0137 #define ST_UART011_DMAWM_RX_32  (5 << 3)
0138 #define ST_UART011_DMAWM_RX_48  (6 << 3)
0139 #define ST_UART011_DMAWM_TX_1   0
0140 #define ST_UART011_DMAWM_TX_2   1
0141 #define ST_UART011_DMAWM_TX_4   2
0142 #define ST_UART011_DMAWM_TX_8   3
0143 #define ST_UART011_DMAWM_TX_16  4
0144 #define ST_UART011_DMAWM_TX_32  5
0145 #define ST_UART011_DMAWM_TX_48  6
0146
0147 #define UART010_IIR_RTIS    0x08
0148 #define UART010_IIR_TIS     0x04
0149 #define UART010_IIR_RIS     0x02
0150 #define UART010_IIR_MIS     0x01
0151
0152 #define UART011_IFLS_RX1_8  (0 << 3)
0153 #define UART011_IFLS_RX2_8  (1 << 3)
0154 #define UART011_IFLS_RX4_8  (2 << 3)
0155 #define UART011_IFLS_RX6_8  (3 << 3)
0156 #define UART011_IFLS_RX7_8  (4 << 3)
0157 #define UART011_IFLS_TX1_8  (0 << 0)
0158 #define UART011_IFLS_TX2_8  (1 << 0)
0159 #define UART011_IFLS_TX4_8  (2 << 0)
0160 #define UART011_IFLS_TX6_8  (3 << 0)
0161 #define UART011_IFLS_TX7_8  (4 << 0)
0162 /* special values for ST vendor with deeper fifo */
0163 #define UART011_IFLS_RX_HALF    (5 << 3)
0164 #define UART011_IFLS_TX_HALF    (5 << 0)
0165
0166 #define UART011_OEIM        (1 << 10)   /* overrun error interrupt mask */
0167 #define UART011_BEIM        (1 << 9)    /* break error interrupt mask */
0168 #define UART011_PEIM        (1 << 8)    /* parity error interrupt mask */
0169 #define UART011_FEIM        (1 << 7)    /* framing error interrupt mask */
0170 #define UART011_RTIM        (1 << 6)    /* receive timeout interrupt mask */
0171 #define UART011_TXIM        (1 << 5)    /* transmit interrupt mask */
0172 #define UART011_RXIM        (1 << 4)    /* receive interrupt mask */
0173 #define UART011_DSRMIM      (1 << 3)    /* DSR interrupt mask */
0174 #define UART011_DCDMIM      (1 << 2)    /* DCD interrupt mask */
0175 #define UART011_CTSMIM      (1 << 1)    /* CTS interrupt mask */
0176 #define UART011_RIMIM       (1 << 0)    /* RI interrupt mask */
0177
0178 #define UART011_OEIS        (1 << 10)   /* overrun error interrupt status */
0179 #define UART011_BEIS        (1 << 9)    /* break error interrupt status */
0180 #define UART011_PEIS        (1 << 8)    /* parity error interrupt status */
0181 #define UART011_FEIS        (1 << 7)    /* framing error interrupt status */
0182 #define UART011_RTIS        (1 << 6)    /* receive timeout interrupt status */
0183 #define UART011_TXIS        (1 << 5)    /* transmit interrupt status */
0184 #define UART011_RXIS        (1 << 4)    /* receive interrupt status */
0185 #define UART011_DSRMIS      (1 << 3)    /* DSR interrupt status */
0186 #define UART011_DCDMIS      (1 << 2)    /* DCD interrupt status */
0187 #define UART011_CTSMIS      (1 << 1)    /* CTS interrupt status */
0188 #define UART011_RIMIS       (1 << 0)    /* RI interrupt status */
0189
0190 #define UART011_OEIC        (1 << 10)   /* overrun error interrupt clear */
0191 #define UART011_BEIC        (1 << 9)    /* break error interrupt clear */
0192 #define UART011_PEIC        (1 << 8)    /* parity error interrupt clear */
0193 #define UART011_FEIC        (1 << 7)    /* framing error interrupt clear */
0194 #define UART011_RTIC        (1 << 6)    /* receive timeout interrupt clear */
0195 #define UART011_TXIC        (1 << 5)    /* transmit interrupt clear */
0196 #define UART011_RXIC        (1 << 4)    /* receive interrupt clear */
0197 #define UART011_DSRMIC      (1 << 3)    /* DSR interrupt clear */
0198 #define UART011_DCDMIC      (1 << 2)    /* DCD interrupt clear */
0199 #define UART011_CTSMIC      (1 << 1)    /* CTS interrupt clear */
0200 #define UART011_RIMIC       (1 << 0)    /* RI interrupt clear */
0201
0202 #define UART011_DMAONERR    (1 << 2)    /* disable dma on error */
0203 #define UART011_TXDMAE      (1 << 1)    /* enable transmit dma */
0204 #define UART011_RXDMAE      (1 << 0)    /* enable receive dma */
0205
0206 #define UART01x_RSR_ANY     (UART01x_RSR_OE|UART01x_RSR_BE|UART01x_RSR_PE|UART01x_RSR_FE)
0207 #define UART01x_FR_MODEM_ANY    (UART01x_FR_DCD|UART01x_FR_DSR|UART01x_FR_CTS)
0208
0209 #ifndef __ASSEMBLY__
0210 struct amba_device; /* in uncompress this is included but amba/bus.h is not */
0211 struct amba_pl010_data {
0212     void (*set_mctrl)(struct amba_device *dev, void __iomem *base, unsigned int mctrl);
0213 };
0214
0215 struct dma_chan;
0216 struct amba_pl011_data {
0217     bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
0218     void *dma_rx_param;
0219     void *dma_tx_param;
0220     bool dma_rx_poll_enable;
0221     unsigned int dma_rx_poll_rate;
0222     unsigned int dma_rx_poll_timeout;
0223         void (*init) (void);
0224     void (*exit) (void);
0225 };
0226 #endif
0227
0228 #endif