linux/amba/pl093.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* linux/amba/pl093.h
0003  *
0004  * Copyright (c) 2008 Simtec Electronics
0005  *  http://armlinux.simtec.co.uk/
0006  *  Ben Dooks <ben@simtec.co.uk>
0007  *
0008  * AMBA PL093 SSMC (synchronous static memory controller)
0009  *  See DDI0236.pdf (r0p4) for more details
0010 */
0011
0012 #define SMB_BANK(x) ((x) * 0x20) /* each bank control set is 0x20 apart */
0013
0014 /* Offsets for SMBxxxxRy registers */
0015
0016 #define SMBIDCYR    (0x00)
0017 #define SMBWSTRDR   (0x04)
0018 #define SMBWSTWRR   (0x08)
0019 #define SMBWSTOENR  (0x0C)
0020 #define SMBWSTWENR  (0x10)
0021 #define SMBCR       (0x14)
0022 #define SMBSR       (0x18)
0023 #define SMBWSTBRDR  (0x1C)
0024
0025 /* Masks for SMB registers */
0026 #define IDCY_MASK   (0xf)
0027 #define WSTRD_MASK  (0xf)
0028 #define WSTWR_MASK  (0xf)
0029 #define WSTOEN_MASK (0xf)
0030 #define WSTWEN_MASK (0xf)
0031
0032 /* Notes from datasheet:
0033  *  WSTOEN <= WSTRD
0034  *  WSTWEN <= WSTWR
0035  *
0036  * WSTOEN is not used with nWAIT
0037  */
0038
0039 /* SMBCR bit definitions */
0040 #define SMBCR_BIWRITEEN     (1 << 21)
0041 #define SMBCR_ADDRVALIDWRITEEN  (1 << 20)
0042 #define SMBCR_SYNCWRITE     (1 << 17)
0043 #define SMBCR_BMWRITE       (1 << 16)
0044 #define SMBCR_WRAPREAD      (1 << 14)
0045 #define SMBCR_BIREADEN      (1 << 13)
0046 #define SMBCR_ADDRVALIDREADEN   (1 << 12)
0047 #define SMBCR_SYNCREAD      (1 << 9)
0048 #define SMBCR_BMREAD        (1 << 8)
0049 #define SMBCR_SMBLSPOL      (1 << 6)
0050 #define SMBCR_WP        (1 << 3)
0051 #define SMBCR_WAITEN        (1 << 2)
0052 #define SMBCR_WAITPOL       (1 << 1)
0053 #define SMBCR_RBLE      (1 << 0)
0054
0055 #define SMBCR_BURSTLENWRITE_MASK    (3 << 18)
0056 #define SMBCR_BURSTLENWRITE_4       (0 << 18)
0057 #define SMBCR_BURSTLENWRITE_8       (1 << 18)
0058 #define SMBCR_BURSTLENWRITE_RESERVED    (2 << 18)
0059 #define SMBCR_BURSTLENWRITE_CONTINUOUS  (3 << 18)
0060
0061 #define SMBCR_BURSTLENREAD_MASK     (3 << 10)
0062 #define SMBCR_BURSTLENREAD_4        (0 << 10)
0063 #define SMBCR_BURSTLENREAD_8        (1 << 10)
0064 #define SMBCR_BURSTLENREAD_16       (2 << 10)
0065 #define SMBCR_BURSTLENREAD_CONTINUOUS   (3 << 10)
0066
0067 #define SMBCR_MW_MASK           (3 << 4)
0068 #define SMBCR_MW_8BIT           (0 << 4)
0069 #define SMBCR_MW_16BIT          (1 << 4)
0070 #define SMBCR_MW_M32BIT         (2 << 4)
0071
0072 /* SSMC status registers */
0073 #define SSMCCSR     (0x200)
0074 #define SSMCCR      (0x204)
0075 #define SSMCITCR    (0x208)
0076 #define SSMCITIP    (0x20C)
0077 #define SSMCITIOP   (0x210)