linux/amba/pl022.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * include/linux/amba/pl022.h
0004  *
0005  * Copyright (C) 2008-2009 ST-Ericsson AB
0006  * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
0007  *
0008  * Author: Linus Walleij <linus.walleij@stericsson.com>
0009  *
0010  * Initial version inspired by:
0011  *  linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
0012  * Initial adoption to PL022 by:
0013  *      Sachin Verma <sachin.verma@st.com>
0014  */
0015
0016 #ifndef _SSP_PL022_H
0017 #define _SSP_PL022_H
0018
0019 #include <linux/types.h>
0020
0021 /**
0022  * whether SSP is in loopback mode or not
0023  */
0024 enum ssp_loopback {
0025     LOOPBACK_DISABLED,
0026     LOOPBACK_ENABLED
0027 };
0028
0029 /**
0030  * enum ssp_interface - interfaces allowed for this SSP Controller
0031  * @SSP_INTERFACE_MOTOROLA_SPI: Motorola Interface
0032  * @SSP_INTERFACE_TI_SYNC_SERIAL: Texas Instrument Synchronous Serial
0033  * interface
0034  * @SSP_INTERFACE_NATIONAL_MICROWIRE: National Semiconductor Microwire
0035  * interface
0036  * @SSP_INTERFACE_UNIDIRECTIONAL: Unidirectional interface (STn8810
0037  * &STn8815 only)
0038  */
0039 enum ssp_interface {
0040     SSP_INTERFACE_MOTOROLA_SPI,
0041     SSP_INTERFACE_TI_SYNC_SERIAL,
0042     SSP_INTERFACE_NATIONAL_MICROWIRE,
0043     SSP_INTERFACE_UNIDIRECTIONAL
0044 };
0045
0046 /**
0047  * enum ssp_hierarchy - whether SSP is configured as Master or Slave
0048  */
0049 enum ssp_hierarchy {
0050     SSP_MASTER,
0051     SSP_SLAVE
0052 };
0053
0054 /**
0055  * enum ssp_clock_params - clock parameters, to set SSP clock at a
0056  * desired freq
0057  */
0058 struct ssp_clock_params {
0059     u8 cpsdvsr; /* value from 2 to 254 (even only!) */
0060     u8 scr;     /* value from 0 to 255 */
0061 };
0062
0063 /**
0064  * enum ssp_rx_endian - endianess of Rx FIFO Data
0065  * this feature is only available in ST versionf of PL022
0066  */
0067 enum ssp_rx_endian {
0068     SSP_RX_MSB,
0069     SSP_RX_LSB
0070 };
0071
0072 /**
0073  * enum ssp_tx_endian - endianess of Tx FIFO Data
0074  */
0075 enum ssp_tx_endian {
0076     SSP_TX_MSB,
0077     SSP_TX_LSB
0078 };
0079
0080 /**
0081  * enum ssp_data_size - number of bits in one data element
0082  */
0083 enum ssp_data_size {
0084     SSP_DATA_BITS_4 = 0x03, SSP_DATA_BITS_5, SSP_DATA_BITS_6,
0085     SSP_DATA_BITS_7, SSP_DATA_BITS_8, SSP_DATA_BITS_9,
0086     SSP_DATA_BITS_10, SSP_DATA_BITS_11, SSP_DATA_BITS_12,
0087     SSP_DATA_BITS_13, SSP_DATA_BITS_14, SSP_DATA_BITS_15,
0088     SSP_DATA_BITS_16, SSP_DATA_BITS_17, SSP_DATA_BITS_18,
0089     SSP_DATA_BITS_19, SSP_DATA_BITS_20, SSP_DATA_BITS_21,
0090     SSP_DATA_BITS_22, SSP_DATA_BITS_23, SSP_DATA_BITS_24,
0091     SSP_DATA_BITS_25, SSP_DATA_BITS_26, SSP_DATA_BITS_27,
0092     SSP_DATA_BITS_28, SSP_DATA_BITS_29, SSP_DATA_BITS_30,
0093     SSP_DATA_BITS_31, SSP_DATA_BITS_32
0094 };
0095
0096 /**
0097  * enum ssp_mode - SSP mode of operation (Communication modes)
0098  */
0099 enum ssp_mode {
0100     INTERRUPT_TRANSFER,
0101     POLLING_TRANSFER,
0102     DMA_TRANSFER
0103 };
0104
0105 /**
0106  * enum ssp_rx_level_trig - receive FIFO watermark level which triggers
0107  * IT: Interrupt fires when _N_ or more elements in RX FIFO.
0108  */
0109 enum ssp_rx_level_trig {
0110     SSP_RX_1_OR_MORE_ELEM,
0111     SSP_RX_4_OR_MORE_ELEM,
0112     SSP_RX_8_OR_MORE_ELEM,
0113     SSP_RX_16_OR_MORE_ELEM,
0114     SSP_RX_32_OR_MORE_ELEM
0115 };
0116
0117 /**
0118  * Transmit FIFO watermark level which triggers (IT Interrupt fires
0119  * when _N_ or more empty locations in TX FIFO)
0120  */
0121 enum ssp_tx_level_trig {
0122     SSP_TX_1_OR_MORE_EMPTY_LOC,
0123     SSP_TX_4_OR_MORE_EMPTY_LOC,
0124     SSP_TX_8_OR_MORE_EMPTY_LOC,
0125     SSP_TX_16_OR_MORE_EMPTY_LOC,
0126     SSP_TX_32_OR_MORE_EMPTY_LOC
0127 };
0128
0129 /**
0130  * enum SPI Clock Phase - clock phase (Motorola SPI interface only)
0131  * @SSP_CLK_FIRST_EDGE: Receive data on first edge transition (actual direction depends on polarity)
0132  * @SSP_CLK_SECOND_EDGE: Receive data on second edge transition (actual direction depends on polarity)
0133  */
0134 enum ssp_spi_clk_phase {
0135     SSP_CLK_FIRST_EDGE,
0136     SSP_CLK_SECOND_EDGE
0137 };
0138
0139 /**
0140  * enum SPI Clock Polarity - clock polarity (Motorola SPI interface only)
0141  * @SSP_CLK_POL_IDLE_LOW: Low inactive level
0142  * @SSP_CLK_POL_IDLE_HIGH: High inactive level
0143  */
0144 enum ssp_spi_clk_pol {
0145     SSP_CLK_POL_IDLE_LOW,
0146     SSP_CLK_POL_IDLE_HIGH
0147 };
0148
0149 /**
0150  * Microwire Conrol Lengths Command size in microwire format
0151  */
0152 enum ssp_microwire_ctrl_len {
0153     SSP_BITS_4 = 0x03, SSP_BITS_5, SSP_BITS_6,
0154     SSP_BITS_7, SSP_BITS_8, SSP_BITS_9,
0155     SSP_BITS_10, SSP_BITS_11, SSP_BITS_12,
0156     SSP_BITS_13, SSP_BITS_14, SSP_BITS_15,
0157     SSP_BITS_16, SSP_BITS_17, SSP_BITS_18,
0158     SSP_BITS_19, SSP_BITS_20, SSP_BITS_21,
0159     SSP_BITS_22, SSP_BITS_23, SSP_BITS_24,
0160     SSP_BITS_25, SSP_BITS_26, SSP_BITS_27,
0161     SSP_BITS_28, SSP_BITS_29, SSP_BITS_30,
0162     SSP_BITS_31, SSP_BITS_32
0163 };
0164
0165 /**
0166  * enum Microwire Wait State
0167  * @SSP_MWIRE_WAIT_ZERO: No wait state inserted after last command bit
0168  * @SSP_MWIRE_WAIT_ONE: One wait state inserted after last command bit
0169  */
0170 enum ssp_microwire_wait_state {
0171     SSP_MWIRE_WAIT_ZERO,
0172     SSP_MWIRE_WAIT_ONE
0173 };
0174
0175 /**
0176  * enum ssp_duplex - whether Full/Half Duplex on microwire, only
0177  * available in the ST Micro variant.
0178  * @SSP_MICROWIRE_CHANNEL_FULL_DUPLEX: SSPTXD becomes bi-directional,
0179  *     SSPRXD not used
0180  * @SSP_MICROWIRE_CHANNEL_HALF_DUPLEX: SSPTXD is an output, SSPRXD is
0181  *     an input.
0182  */
0183 enum ssp_duplex {
0184     SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
0185     SSP_MICROWIRE_CHANNEL_HALF_DUPLEX
0186 };
0187
0188 /**
0189  * enum ssp_clkdelay - an optional clock delay on the feedback clock
0190  * only available in the ST Micro PL023 variant.
0191  * @SSP_FEEDBACK_CLK_DELAY_NONE: no delay, the data coming in from the
0192  * slave is sampled directly
0193  * @SSP_FEEDBACK_CLK_DELAY_1T: the incoming slave data is sampled with
0194  * a delay of T-dt
0195  * @SSP_FEEDBACK_CLK_DELAY_2T: dito with a delay if 2T-dt
0196  * @SSP_FEEDBACK_CLK_DELAY_3T: dito with a delay if 3T-dt
0197  * @SSP_FEEDBACK_CLK_DELAY_4T: dito with a delay if 4T-dt
0198  * @SSP_FEEDBACK_CLK_DELAY_5T: dito with a delay if 5T-dt
0199  * @SSP_FEEDBACK_CLK_DELAY_6T: dito with a delay if 6T-dt
0200  * @SSP_FEEDBACK_CLK_DELAY_7T: dito with a delay if 7T-dt
0201  */
0202 enum ssp_clkdelay {
0203     SSP_FEEDBACK_CLK_DELAY_NONE,
0204     SSP_FEEDBACK_CLK_DELAY_1T,
0205     SSP_FEEDBACK_CLK_DELAY_2T,
0206     SSP_FEEDBACK_CLK_DELAY_3T,
0207     SSP_FEEDBACK_CLK_DELAY_4T,
0208     SSP_FEEDBACK_CLK_DELAY_5T,
0209     SSP_FEEDBACK_CLK_DELAY_6T,
0210     SSP_FEEDBACK_CLK_DELAY_7T
0211 };
0212
0213 /**
0214  * CHIP select/deselect commands
0215  */
0216 enum ssp_chip_select {
0217     SSP_CHIP_SELECT,
0218     SSP_CHIP_DESELECT
0219 };
0220
0221
0222 struct dma_chan;
0223 /**
0224  * struct pl022_ssp_master - device.platform_data for SPI controller devices.
0225  * @bus_id: identifier for this bus
0226  * @enable_dma: if true enables DMA driven transfers.
0227  * @dma_rx_param: parameter to locate an RX DMA channel.
0228  * @dma_tx_param: parameter to locate a TX DMA channel.
0229  * @autosuspend_delay: delay in ms following transfer completion before the
0230  *     runtime power management system suspends the device. A setting of 0
0231  *     indicates no delay and the device will be suspended immediately.
0232  * @rt: indicates the controller should run the message pump with realtime
0233  *     priority to minimise the transfer latency on the bus.
0234  */
0235 struct pl022_ssp_controller {
0236     u16 bus_id;
0237     u8 enable_dma:1;
0238     bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
0239     void *dma_rx_param;
0240     void *dma_tx_param;
0241     int autosuspend_delay;
0242     bool rt;
0243 };
0244
0245 /**
0246  * struct ssp_config_chip - spi_board_info.controller_data for SPI
0247  * slave devices, copied to spi_device.controller_data.
0248  *
0249  * @iface: Interface type(Motorola, TI, Microwire, Universal)
0250  * @hierarchy: sets whether interface is master or slave
0251  * @slave_tx_disable: SSPTXD is disconnected (in slave mode only)
0252  * @clk_freq: Tune freq parameters of SSP(when in master mode)
0253  * @com_mode: communication mode: polling, Interrupt or DMA
0254  * @rx_lev_trig: Rx FIFO watermark level (for IT & DMA mode)
0255  * @tx_lev_trig: Tx FIFO watermark level (for IT & DMA mode)
0256  * @ctrl_len: Microwire interface: Control length
0257  * @wait_state: Microwire interface: Wait state
0258  * @duplex: Microwire interface: Full/Half duplex
0259  * @clkdelay: on the PL023 variant, the delay in feeback clock cycles
0260  * before sampling the incoming line
0261  */
0262 struct pl022_config_chip {
0263     enum ssp_interface iface;
0264     enum ssp_hierarchy hierarchy;
0265     bool slave_tx_disable;
0266     struct ssp_clock_params clk_freq;
0267     enum ssp_mode com_mode;
0268     enum ssp_rx_level_trig rx_lev_trig;
0269     enum ssp_tx_level_trig tx_lev_trig;
0270     enum ssp_microwire_ctrl_len ctrl_len;
0271     enum ssp_microwire_wait_state wait_state;
0272     enum ssp_duplex duplex;
0273     enum ssp_clkdelay clkdelay;
0274 };
0275
0276 #endif /* _SSP_PL022_H */