linux/amba/clcd-regs.h

0001 /*
0002  * David A Rusling
0003  *
0004  * Copyright (C) 2001 ARM Limited
0005  *
0006  * This file is subject to the terms and conditions of the GNU General Public
0007  * License.  See the file COPYING in the main directory of this archive
0008  * for more details.
0009  */
0010
0011 #ifndef AMBA_CLCD_REGS_H
0012 #define AMBA_CLCD_REGS_H
0013
0014 /*
0015  * CLCD Controller Internal Register addresses
0016  */
0017 #define CLCD_TIM0       0x00000000
0018 #define CLCD_TIM1       0x00000004
0019 #define CLCD_TIM2       0x00000008
0020 #define CLCD_TIM3       0x0000000c
0021 #define CLCD_UBAS       0x00000010
0022 #define CLCD_LBAS       0x00000014
0023
0024 #define CLCD_PL110_IENB     0x00000018
0025 #define CLCD_PL110_CNTL     0x0000001c
0026 #define CLCD_PL110_STAT     0x00000020
0027 #define CLCD_PL110_INTR     0x00000024
0028 #define CLCD_PL110_UCUR     0x00000028
0029 #define CLCD_PL110_LCUR     0x0000002C
0030
0031 #define CLCD_PL111_CNTL     0x00000018
0032 #define CLCD_PL111_IENB     0x0000001c
0033 #define CLCD_PL111_RIS      0x00000020
0034 #define CLCD_PL111_MIS      0x00000024
0035 #define CLCD_PL111_ICR      0x00000028
0036 #define CLCD_PL111_UCUR     0x0000002c
0037 #define CLCD_PL111_LCUR     0x00000030
0038
0039 #define CLCD_PALL       0x00000200
0040 #define CLCD_PALETTE        0x00000200
0041
0042 #define TIM2_PCD_LO_MASK    GENMASK(4, 0)
0043 #define TIM2_PCD_LO_BITS    5
0044 #define TIM2_CLKSEL     (1 << 5)
0045 #define TIM2_ACB_MASK       GENMASK(10, 6)
0046 #define TIM2_IVS        (1 << 11)
0047 #define TIM2_IHS        (1 << 12)
0048 #define TIM2_IPC        (1 << 13)
0049 #define TIM2_IOE        (1 << 14)
0050 #define TIM2_BCD        (1 << 26)
0051 #define TIM2_PCD_HI_MASK    GENMASK(31, 27)
0052 #define TIM2_PCD_HI_BITS    5
0053 #define TIM2_PCD_HI_SHIFT   27
0054
0055 #define CNTL_LCDEN      (1 << 0)
0056 #define CNTL_LCDBPP1        (0 << 1)
0057 #define CNTL_LCDBPP2        (1 << 1)
0058 #define CNTL_LCDBPP4        (2 << 1)
0059 #define CNTL_LCDBPP8        (3 << 1)
0060 #define CNTL_LCDBPP16       (4 << 1)
0061 #define CNTL_LCDBPP16_565   (6 << 1)
0062 #define CNTL_LCDBPP16_444   (7 << 1)
0063 #define CNTL_LCDBPP24       (5 << 1)
0064 #define CNTL_LCDBW      (1 << 4)
0065 #define CNTL_LCDTFT     (1 << 5)
0066 #define CNTL_LCDMONO8       (1 << 6)
0067 #define CNTL_LCDDUAL        (1 << 7)
0068 #define CNTL_BGR        (1 << 8)
0069 #define CNTL_BEBO       (1 << 9)
0070 #define CNTL_BEPO       (1 << 10)
0071 #define CNTL_LCDPWR     (1 << 11)
0072 #define CNTL_LCDVCOMP(x)    ((x) << 12)
0073 #define CNTL_LDMAFIFOTIME   (1 << 15)
0074 #define CNTL_WATERMARK      (1 << 16)
0075
0076 /* ST Microelectronics variant bits */
0077 #define CNTL_ST_1XBPP_444   0x0
0078 #define CNTL_ST_1XBPP_5551  (1 << 17)
0079 #define CNTL_ST_1XBPP_565   (1 << 18)
0080 #define CNTL_ST_CDWID_12    0x0
0081 #define CNTL_ST_CDWID_16    (1 << 19)
0082 #define CNTL_ST_CDWID_18    (1 << 20)
0083 #define CNTL_ST_CDWID_24    ((1 << 19)|(1 << 20))
0084 #define CNTL_ST_CEAEN       (1 << 21)
0085 #define CNTL_ST_LCDBPP24_PACKED (6 << 1)
0086
0087 #endif /* AMBA_CLCD_REGS_H */