include/linux/adreno-smmu-priv.h

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2020 Google, Inc
0004  */
0005
0006 #ifndef __ADRENO_SMMU_PRIV_H
0007 #define __ADRENO_SMMU_PRIV_H
0008
0009 #include <linux/io-pgtable.h>
0010
0011 /**
0012  * struct adreno_smmu_fault_info - container for key fault information
0013  *
0014  * @far: The faulting IOVA from ARM_SMMU_CB_FAR
0015  * @ttbr0: The current TTBR0 pagetable from ARM_SMMU_CB_TTBR0
0016  * @contextidr: The value of ARM_SMMU_CB_CONTEXTIDR
0017  * @fsr: The fault status from ARM_SMMU_CB_FSR
0018  * @fsynr0: The value of FSYNR0 from ARM_SMMU_CB_FSYNR0
0019  * @fsynr1: The value of FSYNR1 from ARM_SMMU_CB_FSYNR0
0020  * @cbfrsynra: The value of CBFRSYNRA from ARM_SMMU_GR1_CBFRSYNRA(idx)
0021  *
0022  * This struct passes back key page fault information to the GPU driver
0023  * through the get_fault_info function pointer.
0024  * The GPU driver can use this information to print informative
0025  * log messages and provide deeper GPU specific insight into the fault.
0026  */
0027 struct adreno_smmu_fault_info {
0028     u64 far;
0029     u64 ttbr0;
0030     u32 contextidr;
0031     u32 fsr;
0032     u32 fsynr0;
0033     u32 fsynr1;
0034     u32 cbfrsynra;
0035 };
0036
0037 /**
0038  * struct adreno_smmu_priv - private interface between adreno-smmu and GPU
0039  *
0040  * @cookie:        An opque token provided by adreno-smmu and passed
0041  *                 back into the callbacks
0042  * @get_ttbr1_cfg: Get the TTBR1 config for the GPUs context-bank
0043  * @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank.  A
0044  *                 NULL config disables TTBR0 translation, otherwise
0045  *                 TTBR0 translation is enabled with the specified cfg
0046  * @get_fault_info: Called by the GPU fault handler to get information about
0047  *                  the fault
0048  * @set_stall:     Configure whether stall on fault (CFCFG) is enabled.  Call
0049  *                 before set_ttbr0_cfg().  If stalling on fault is enabled,
0050  *                 the GPU driver must call resume_translation()
0051  * @resume_translation: Resume translation after a fault
0052  *
0053  *
0054  * The GPU driver (drm/msm) and adreno-smmu work together for controlling
0055  * the GPU's SMMU instance.  This is by necessity, as the GPU is directly
0056  * updating the SMMU for context switches, while on the other hand we do
0057  * not want to duplicate all of the initial setup logic from arm-smmu.
0058  *
0059  * This private interface is used for the two drivers to coordinate.  The
0060  * cookie and callback functions are populated when the GPU driver attaches
0061  * it's domain.
0062  */
0063 struct adreno_smmu_priv {
0064     const void *cookie;
0065     const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie);
0066     int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg);
0067     void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info);
0068     void (*set_stall)(const void *cookie, bool enabled);
0069     void (*resume_translation)(const void *cookie, bool terminate);
0070 };
0071
0072 #endif /* __ADRENO_SMMU_PRIV_H */