include/kvm/arm_vgic.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2015, 2016 ARM Ltd.
0004  */
0005 #ifndef __KVM_ARM_VGIC_H
0006 #define __KVM_ARM_VGIC_H
0007
0008 #include <linux/bits.h>
0009 #include <linux/kvm.h>
0010 #include <linux/irqreturn.h>
0011 #include <linux/kref.h>
0012 #include <linux/mutex.h>
0013 #include <linux/spinlock.h>
0014 #include <linux/static_key.h>
0015 #include <linux/types.h>
0016 #include <kvm/iodev.h>
0017 #include <linux/list.h>
0018 #include <linux/jump_label.h>
0019
0020 #include <linux/irqchip/arm-gic-v4.h>
0021
0022 #define VGIC_V3_MAX_CPUS    512
0023 #define VGIC_V2_MAX_CPUS    8
0024 #define VGIC_NR_IRQS_LEGACY     256
0025 #define VGIC_NR_SGIS        16
0026 #define VGIC_NR_PPIS        16
0027 #define VGIC_NR_PRIVATE_IRQS    (VGIC_NR_SGIS + VGIC_NR_PPIS)
0028 #define VGIC_MAX_PRIVATE    (VGIC_NR_PRIVATE_IRQS - 1)
0029 #define VGIC_MAX_SPI        1019
0030 #define VGIC_MAX_RESERVED   1023
0031 #define VGIC_MIN_LPI        8192
0032 #define KVM_IRQCHIP_NUM_PINS    (1020 - 32)
0033
0034 #define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS)
0035 #define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \
0036              (irq) <= VGIC_MAX_SPI)
0037
0038 enum vgic_type {
0039     VGIC_V2,        /* Good ol' GICv2 */
0040     VGIC_V3,        /* New fancy GICv3 */
0041 };
0042
0043 /* same for all guests, as depending only on the _host's_ GIC model */
0044 struct vgic_global {
0045     /* type of the host GIC */
0046     enum vgic_type      type;
0047
0048     /* Physical address of vgic virtual cpu interface */
0049     phys_addr_t     vcpu_base;
0050
0051     /* GICV mapping, kernel VA */
0052     void __iomem        *vcpu_base_va;
0053     /* GICV mapping, HYP VA */
0054     void __iomem        *vcpu_hyp_va;
0055
0056     /* virtual control interface mapping, kernel VA */
0057     void __iomem        *vctrl_base;
0058     /* virtual control interface mapping, HYP VA */
0059     void __iomem        *vctrl_hyp;
0060
0061     /* Number of implemented list registers */
0062     int         nr_lr;
0063
0064     /* Maintenance IRQ number */
0065     unsigned int        maint_irq;
0066
0067     /* maximum number of VCPUs allowed (GICv2 limits us to 8) */
0068     int         max_gic_vcpus;
0069
0070     /* Only needed for the legacy KVM_CREATE_IRQCHIP */
0071     bool            can_emulate_gicv2;
0072
0073     /* Hardware has GICv4? */
0074     bool            has_gicv4;
0075     bool            has_gicv4_1;
0076
0077     /* Pseudo GICv3 from outer space */
0078     bool            no_hw_deactivation;
0079
0080     /* GIC system register CPU interface */
0081     struct static_key_false gicv3_cpuif;
0082
0083     u32         ich_vtr_el2;
0084 };
0085
0086 extern struct vgic_global kvm_vgic_global_state;
0087
0088 #define VGIC_V2_MAX_LRS     (1 << 6)
0089 #define VGIC_V3_MAX_LRS     16
0090 #define VGIC_V3_LR_INDEX(lr)    (VGIC_V3_MAX_LRS - 1 - lr)
0091
0092 enum vgic_irq_config {
0093     VGIC_CONFIG_EDGE = 0,
0094     VGIC_CONFIG_LEVEL
0095 };
0096
0097 /*
0098  * Per-irq ops overriding some common behavious.
0099  *
0100  * Always called in non-preemptible section and the functions can use
0101  * kvm_arm_get_running_vcpu() to get the vcpu pointer for private IRQs.
0102  */
0103 struct irq_ops {
0104     /* Per interrupt flags for special-cased interrupts */
0105     unsigned long flags;
0106
0107 #define VGIC_IRQ_SW_RESAMPLE    BIT(0)  /* Clear the active state for resampling */
0108
0109     /*
0110      * Callback function pointer to in-kernel devices that can tell us the
0111      * state of the input level of mapped level-triggered IRQ faster than
0112      * peaking into the physical GIC.
0113      */
0114     bool (*get_input_level)(int vintid);
0115 };
0116
0117 struct vgic_irq {
0118     raw_spinlock_t irq_lock;    /* Protects the content of the struct */
0119     struct list_head lpi_list;  /* Used to link all LPIs together */
0120     struct list_head ap_list;
0121
0122     struct kvm_vcpu *vcpu;      /* SGIs and PPIs: The VCPU
0123                      * SPIs and LPIs: The VCPU whose ap_list
0124                      * this is queued on.
0125                      */
0126
0127     struct kvm_vcpu *target_vcpu;   /* The VCPU that this interrupt should
0128                      * be sent to, as a result of the
0129                      * targets reg (v2) or the
0130                      * affinity reg (v3).
0131                      */
0132
0133     u32 intid;          /* Guest visible INTID */
0134     bool line_level;        /* Level only */
0135     bool pending_latch;     /* The pending latch state used to calculate
0136                      * the pending state for both level
0137                      * and edge triggered IRQs. */
0138     bool active;            /* not used for LPIs */
0139     bool enabled;
0140     bool hw;            /* Tied to HW IRQ */
0141     struct kref refcount;       /* Used for LPIs */
0142     u32 hwintid;            /* HW INTID number */
0143     unsigned int host_irq;      /* linux irq corresponding to hwintid */
0144     union {
0145         u8 targets;         /* GICv2 target VCPUs mask */
0146         u32 mpidr;          /* GICv3 target VCPU */
0147     };
0148     u8 source;          /* GICv2 SGIs only */
0149     u8 active_source;       /* GICv2 SGIs only */
0150     u8 priority;
0151     u8 group;           /* 0 == group 0, 1 == group 1 */
0152     enum vgic_irq_config config;    /* Level or edge */
0153
0154     struct irq_ops *ops;
0155
0156     void *owner;            /* Opaque pointer to reserve an interrupt
0157                        for in-kernel devices. */
0158 };
0159
0160 static inline bool vgic_irq_needs_resampling(struct vgic_irq *irq)
0161 {
0162     return irq->ops && (irq->ops->flags & VGIC_IRQ_SW_RESAMPLE);
0163 }
0164
0165 struct vgic_register_region;
0166 struct vgic_its;
0167
0168 enum iodev_type {
0169     IODEV_CPUIF,
0170     IODEV_DIST,
0171     IODEV_REDIST,
0172     IODEV_ITS
0173 };
0174
0175 struct vgic_io_device {
0176     gpa_t base_addr;
0177     union {
0178         struct kvm_vcpu *redist_vcpu;
0179         struct vgic_its *its;
0180     };
0181     const struct vgic_register_region *regions;
0182     enum iodev_type iodev_type;
0183     int nr_regions;
0184     struct kvm_io_device dev;
0185 };
0186
0187 struct vgic_its {
0188     /* The base address of the ITS control register frame */
0189     gpa_t           vgic_its_base;
0190
0191     bool            enabled;
0192     struct vgic_io_device   iodev;
0193     struct kvm_device   *dev;
0194
0195     /* These registers correspond to GITS_BASER{0,1} */
0196     u64         baser_device_table;
0197     u64         baser_coll_table;
0198
0199     /* Protects the command queue */
0200     struct mutex        cmd_lock;
0201     u64         cbaser;
0202     u32         creadr;
0203     u32         cwriter;
0204
0205     /* migration ABI revision in use */
0206     u32         abi_rev;
0207
0208     /* Protects the device and collection lists */
0209     struct mutex        its_lock;
0210     struct list_head    device_list;
0211     struct list_head    collection_list;
0212 };
0213
0214 struct vgic_state_iter;
0215
0216 struct vgic_redist_region {
0217     u32 index;
0218     gpa_t base;
0219     u32 count; /* number of redistributors or 0 if single region */
0220     u32 free_index; /* index of the next free redistributor */
0221     struct list_head list;
0222 };
0223
0224 struct vgic_dist {
0225     bool            in_kernel;
0226     bool            ready;
0227     bool            initialized;
0228
0229     /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
0230     u32         vgic_model;
0231
0232     /* Implementation revision as reported in the GICD_IIDR */
0233     u32         implementation_rev;
0234 #define KVM_VGIC_IMP_REV_2  2 /* GICv2 restorable groups */
0235 #define KVM_VGIC_IMP_REV_3  3 /* GICv3 GICR_CTLR.{IW,CES,RWP} */
0236 #define KVM_VGIC_IMP_REV_LATEST KVM_VGIC_IMP_REV_3
0237
0238     /* Userspace can write to GICv2 IGROUPR */
0239     bool            v2_groups_user_writable;
0240
0241     /* Do injected MSIs require an additional device ID? */
0242     bool            msis_require_devid;
0243
0244     int         nr_spis;
0245
0246     /* base addresses in guest physical address space: */
0247     gpa_t           vgic_dist_base;     /* distributor */
0248     union {
0249         /* either a GICv2 CPU interface */
0250         gpa_t           vgic_cpu_base;
0251         /* or a number of GICv3 redistributor regions */
0252         struct list_head rd_regions;
0253     };
0254
0255     /* distributor enabled */
0256     bool            enabled;
0257
0258     /* Wants SGIs without active state */
0259     bool            nassgireq;
0260
0261     struct vgic_irq     *spis;
0262
0263     struct vgic_io_device   dist_iodev;
0264
0265     bool            has_its;
0266
0267     /*
0268      * Contains the attributes and gpa of the LPI configuration table.
0269      * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share
0270      * one address across all redistributors.
0271      * GICv3 spec: IHI 0069E 6.1.1 "LPI Configuration tables"
0272      */
0273     u64         propbaser;
0274
0275     /* Protects the lpi_list and the count value below. */
0276     raw_spinlock_t      lpi_list_lock;
0277     struct list_head    lpi_list_head;
0278     int         lpi_list_count;
0279
0280     /* LPI translation cache */
0281     struct list_head    lpi_translation_cache;
0282
0283     /* used by vgic-debug */
0284     struct vgic_state_iter *iter;
0285
0286     /*
0287      * GICv4 ITS per-VM data, containing the IRQ domain, the VPE
0288      * array, the property table pointer as well as allocation
0289      * data. This essentially ties the Linux IRQ core and ITS
0290      * together, and avoids leaking KVM's data structures anywhere
0291      * else.
0292      */
0293     struct its_vm       its_vm;
0294 };
0295
0296 struct vgic_v2_cpu_if {
0297     u32     vgic_hcr;
0298     u32     vgic_vmcr;
0299     u32     vgic_apr;
0300     u32     vgic_lr[VGIC_V2_MAX_LRS];
0301
0302     unsigned int used_lrs;
0303 };
0304
0305 struct vgic_v3_cpu_if {
0306     u32     vgic_hcr;
0307     u32     vgic_vmcr;
0308     u32     vgic_sre;   /* Restored only, change ignored */
0309     u32     vgic_ap0r[4];
0310     u32     vgic_ap1r[4];
0311     u64     vgic_lr[VGIC_V3_MAX_LRS];
0312
0313     /*
0314      * GICv4 ITS per-VPE data, containing the doorbell IRQ, the
0315      * pending table pointer, the its_vm pointer and a few other
0316      * HW specific things. As for the its_vm structure, this is
0317      * linking the Linux IRQ subsystem and the ITS together.
0318      */
0319     struct its_vpe  its_vpe;
0320
0321     unsigned int used_lrs;
0322 };
0323
0324 struct vgic_cpu {
0325     /* CPU vif control registers for world switch */
0326     union {
0327         struct vgic_v2_cpu_if   vgic_v2;
0328         struct vgic_v3_cpu_if   vgic_v3;
0329     };
0330
0331     struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];
0332
0333     raw_spinlock_t ap_list_lock;    /* Protects the ap_list */
0334
0335     /*
0336      * List of IRQs that this VCPU should consider because they are either
0337      * Active or Pending (hence the name; AP list), or because they recently
0338      * were one of the two and need to be migrated off this list to another
0339      * VCPU.
0340      */
0341     struct list_head ap_list_head;
0342
0343     /*
0344      * Members below are used with GICv3 emulation only and represent
0345      * parts of the redistributor.
0346      */
0347     struct vgic_io_device   rd_iodev;
0348     struct vgic_redist_region *rdreg;
0349     u32 rdreg_index;
0350     atomic_t syncr_busy;
0351
0352     /* Contains the attributes and gpa of the LPI pending tables. */
0353     u64 pendbaser;
0354     /* GICR_CTLR.{ENABLE_LPIS,RWP} */
0355     atomic_t ctlr;
0356
0357     /* Cache guest priority bits */
0358     u32 num_pri_bits;
0359
0360     /* Cache guest interrupt ID bits */
0361     u32 num_id_bits;
0362 };
0363
0364 extern struct static_key_false vgic_v2_cpuif_trap;
0365 extern struct static_key_false vgic_v3_cpuif_trap;
0366
0367 int kvm_set_legacy_vgic_v2_addr(struct kvm *kvm, struct kvm_arm_device_addr *dev_addr);
0368 void kvm_vgic_early_init(struct kvm *kvm);
0369 int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
0370 int kvm_vgic_create(struct kvm *kvm, u32 type);
0371 void kvm_vgic_destroy(struct kvm *kvm);
0372 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
0373 int kvm_vgic_map_resources(struct kvm *kvm);
0374 int kvm_vgic_hyp_init(void);
0375 void kvm_vgic_init_cpu_hardware(void);
0376
0377 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
0378             bool level, void *owner);
0379 int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq,
0380               u32 vintid, struct irq_ops *ops);
0381 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid);
0382 bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid);
0383
0384 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
0385
0386 void kvm_vgic_load(struct kvm_vcpu *vcpu);
0387 void kvm_vgic_put(struct kvm_vcpu *vcpu);
0388 void kvm_vgic_vmcr_sync(struct kvm_vcpu *vcpu);
0389
0390 #define irqchip_in_kernel(k)    (!!((k)->arch.vgic.in_kernel))
0391 #define vgic_initialized(k) ((k)->arch.vgic.initialized)
0392 #define vgic_ready(k)       ((k)->arch.vgic.ready)
0393 #define vgic_valid_spi(k, i)    (((i) >= VGIC_NR_PRIVATE_IRQS) && \
0394             ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
0395
0396 bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
0397 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
0398 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
0399 void kvm_vgic_reset_mapped_irq(struct kvm_vcpu *vcpu, u32 vintid);
0400
0401 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1);
0402
0403 /**
0404  * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
0405  *
0406  * The host's GIC naturally limits the maximum amount of VCPUs a guest
0407  * can use.
0408  */
0409 static inline int kvm_vgic_get_max_vcpus(void)
0410 {
0411     return kvm_vgic_global_state.max_gic_vcpus;
0412 }
0413
0414 /**
0415  * kvm_vgic_setup_default_irq_routing:
0416  * Setup a default flat gsi routing table mapping all SPIs
0417  */
0418 int kvm_vgic_setup_default_irq_routing(struct kvm *kvm);
0419
0420 int kvm_vgic_set_owner(struct kvm_vcpu *vcpu, unsigned int intid, void *owner);
0421
0422 struct kvm_kernel_irq_routing_entry;
0423
0424 int kvm_vgic_v4_set_forwarding(struct kvm *kvm, int irq,
0425                    struct kvm_kernel_irq_routing_entry *irq_entry);
0426
0427 int kvm_vgic_v4_unset_forwarding(struct kvm *kvm, int irq,
0428                  struct kvm_kernel_irq_routing_entry *irq_entry);
0429
0430 int vgic_v4_load(struct kvm_vcpu *vcpu);
0431 void vgic_v4_commit(struct kvm_vcpu *vcpu);
0432 int vgic_v4_put(struct kvm_vcpu *vcpu, bool need_db);
0433
0434 #endif /* __KVM_ARM_VGIC_H */