0001
0002
0003
0004
0005
0006
0007 #ifndef __ASM_ARM_KVM_PMU_H
0008 #define __ASM_ARM_KVM_PMU_H
0009
0010 #include <linux/perf_event.h>
0011 #include <asm/perf_event.h>
0012
0013 #define ARMV8_PMU_CYCLE_IDX (ARMV8_PMU_MAX_COUNTERS - 1)
0014 #define ARMV8_PMU_MAX_COUNTER_PAIRS ((ARMV8_PMU_MAX_COUNTERS + 1) >> 1)
0015
0016 #ifdef CONFIG_HW_PERF_EVENTS
0017
0018 struct kvm_pmc {
0019 u8 idx;
0020 struct perf_event *perf_event;
0021 };
0022
0023 struct kvm_pmu_events {
0024 u32 events_host;
0025 u32 events_guest;
0026 };
0027
0028 struct kvm_pmu {
0029 struct irq_work overflow_work;
0030 struct kvm_pmu_events events;
0031 struct kvm_pmc pmc[ARMV8_PMU_MAX_COUNTERS];
0032 DECLARE_BITMAP(chained, ARMV8_PMU_MAX_COUNTER_PAIRS);
0033 int irq_num;
0034 bool created;
0035 bool irq_level;
0036 };
0037
0038 struct arm_pmu_entry {
0039 struct list_head entry;
0040 struct arm_pmu *arm_pmu;
0041 };
0042
0043 DECLARE_STATIC_KEY_FALSE(kvm_arm_pmu_available);
0044
0045 static __always_inline bool kvm_arm_support_pmu_v3(void)
0046 {
0047 return static_branch_likely(&kvm_arm_pmu_available);
0048 }
0049
0050 #define kvm_arm_pmu_irq_initialized(v) ((v)->arch.pmu.irq_num >= VGIC_NR_SGIS)
0051 u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
0052 void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val);
0053 u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu);
0054 u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1);
0055 void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu);
0056 void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu);
0057 void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu);
0058 void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val);
0059 void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val);
0060 void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu);
0061 void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu);
0062 bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu);
0063 void kvm_pmu_update_run(struct kvm_vcpu *vcpu);
0064 void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val);
0065 void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val);
0066 void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
0067 u64 select_idx);
0068 int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu,
0069 struct kvm_device_attr *attr);
0070 int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu,
0071 struct kvm_device_attr *attr);
0072 int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu,
0073 struct kvm_device_attr *attr);
0074 int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu);
0075
0076 struct kvm_pmu_events *kvm_get_pmu_events(void);
0077 void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu);
0078 void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu);
0079
0080 #define kvm_vcpu_has_pmu(vcpu) \
0081 (test_bit(KVM_ARM_VCPU_PMU_V3, (vcpu)->arch.features))
0082
0083
0084
0085
0086
0087
0088 #define kvm_pmu_update_vcpu_events(vcpu) \
0089 do { \
0090 if (!has_vhe() && kvm_vcpu_has_pmu(vcpu)) \
0091 vcpu->arch.pmu.events = *kvm_get_pmu_events(); \
0092 } while (0)
0093
0094 #else
0095 struct kvm_pmu {
0096 };
0097
0098 static inline bool kvm_arm_support_pmu_v3(void)
0099 {
0100 return false;
0101 }
0102
0103 #define kvm_arm_pmu_irq_initialized(v) (false)
0104 static inline u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu,
0105 u64 select_idx)
0106 {
0107 return 0;
0108 }
0109 static inline void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu,
0110 u64 select_idx, u64 val) {}
0111 static inline u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
0112 {
0113 return 0;
0114 }
0115 static inline void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu) {}
0116 static inline void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {}
0117 static inline void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) {}
0118 static inline void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val) {}
0119 static inline void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val) {}
0120 static inline void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {}
0121 static inline void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu) {}
0122 static inline bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu)
0123 {
0124 return false;
0125 }
0126 static inline void kvm_pmu_update_run(struct kvm_vcpu *vcpu) {}
0127 static inline void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) {}
0128 static inline void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) {}
0129 static inline void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
0130 u64 data, u64 select_idx) {}
0131 static inline int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu,
0132 struct kvm_device_attr *attr)
0133 {
0134 return -ENXIO;
0135 }
0136 static inline int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu,
0137 struct kvm_device_attr *attr)
0138 {
0139 return -ENXIO;
0140 }
0141 static inline int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu,
0142 struct kvm_device_attr *attr)
0143 {
0144 return -ENXIO;
0145 }
0146 static inline int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu)
0147 {
0148 return 0;
0149 }
0150 static inline u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1)
0151 {
0152 return 0;
0153 }
0154
0155 #define kvm_vcpu_has_pmu(vcpu) ({ false; })
0156 static inline void kvm_pmu_update_vcpu_events(struct kvm_vcpu *vcpu) {}
0157 static inline void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu) {}
0158 static inline void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu) {}
0159
0160 #endif
0161
0162 #endif