dt-bindings/reset/stm32mp13-resets.h

0001 /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
0002 /*
0003  * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
0004  * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
0005  */
0006
0007 #ifndef _DT_BINDINGS_STM32MP13_RESET_H_
0008 #define _DT_BINDINGS_STM32MP13_RESET_H_
0009
0010 #define TIM2_R      13568
0011 #define TIM3_R      13569
0012 #define TIM4_R      13570
0013 #define TIM5_R      13571
0014 #define TIM6_R      13572
0015 #define TIM7_R      13573
0016 #define LPTIM1_R    13577
0017 #define SPI2_R      13579
0018 #define SPI3_R      13580
0019 #define USART3_R    13583
0020 #define UART4_R     13584
0021 #define UART5_R     13585
0022 #define UART7_R     13586
0023 #define UART8_R     13587
0024 #define I2C1_R      13589
0025 #define I2C2_R      13590
0026 #define SPDIF_R     13594
0027 #define TIM1_R      13632
0028 #define TIM8_R      13633
0029 #define SPI1_R      13640
0030 #define USART6_R    13645
0031 #define SAI1_R      13648
0032 #define SAI2_R      13649
0033 #define DFSDM_R     13652
0034 #define FDCAN_R     13656
0035 #define LPTIM2_R    13696
0036 #define LPTIM3_R    13697
0037 #define LPTIM4_R    13698
0038 #define LPTIM5_R    13699
0039 #define SYSCFG_R    13707
0040 #define VREF_R      13709
0041 #define DTS_R       13712
0042 #define PMBCTRL_R   13713
0043 #define LTDC_R      13760
0044 #define DCMIPP_R    13761
0045 #define DDRPERFM_R  13768
0046 #define USBPHY_R    13776
0047 #define STGEN_R     13844
0048 #define USART1_R    13888
0049 #define USART2_R    13889
0050 #define SPI4_R      13890
0051 #define SPI5_R      13891
0052 #define I2C3_R      13892
0053 #define I2C4_R      13893
0054 #define I2C5_R      13894
0055 #define TIM12_R     13895
0056 #define TIM13_R     13896
0057 #define TIM14_R     13897
0058 #define TIM15_R     13898
0059 #define TIM16_R     13899
0060 #define TIM17_R     13900
0061 #define DMA1_R      13952
0062 #define DMA2_R      13953
0063 #define DMAMUX1_R   13954
0064 #define DMA3_R      13955
0065 #define DMAMUX2_R   13956
0066 #define ADC1_R      13957
0067 #define ADC2_R      13958
0068 #define USBO_R      13960
0069 #define GPIOA_R     14080
0070 #define GPIOB_R     14081
0071 #define GPIOC_R     14082
0072 #define GPIOD_R     14083
0073 #define GPIOE_R     14084
0074 #define GPIOF_R     14085
0075 #define GPIOG_R     14086
0076 #define GPIOH_R     14087
0077 #define GPIOI_R     14088
0078 #define TSC_R       14095
0079 #define PKA_R       14146
0080 #define SAES_R      14147
0081 #define CRYP1_R     14148
0082 #define HASH1_R     14149
0083 #define RNG1_R      14150
0084 #define AXIMC_R     14160
0085 #define MDMA_R      14208
0086 #define MCE_R       14209
0087 #define ETH1MAC_R   14218
0088 #define FMC_R       14220
0089 #define QSPI_R      14222
0090 #define SDMMC1_R    14224
0091 #define SDMMC2_R    14225
0092 #define CRC1_R      14228
0093 #define USBH_R      14232
0094 #define ETH2MAC_R   14238
0095
0096 /* SCMI reset domain identifiers */
0097 #define RST_SCMI_LTDC       0
0098 #define RST_SCMI_MDMA       1
0099
0100 #endif /* _DT_BINDINGS_STM32MP13_RESET_H_ */