dt-bindings/reset/mt8195-resets.h

0001 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/
0002 /*
0003  * Copyright (c) 2021 MediaTek Inc.
0004  * Author: Christine Zhu <christine.zhu@mediatek.com>
0005  */
0006
0007 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195
0008 #define _DT_BINDINGS_RESET_CONTROLLER_MT8195
0009
0010 /* TOPRGU resets */
0011 #define MT8195_TOPRGU_CONN_MCU_SW_RST          0
0012 #define MT8195_TOPRGU_INFRA_GRST_SW_RST        1
0013 #define MT8195_TOPRGU_APU_SW_RST               2
0014 #define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST     6
0015 #define MT8195_TOPRGU_MMSYS_SW_RST             7
0016 #define MT8195_TOPRGU_MFG_SW_RST               8
0017 #define MT8195_TOPRGU_VENC_SW_RST              9
0018 #define MT8195_TOPRGU_VDEC_SW_RST              10
0019 #define MT8195_TOPRGU_IMG_SW_RST               11
0020 #define MT8195_TOPRGU_APMIXEDSYS_SW_RST        13
0021 #define MT8195_TOPRGU_AUDIO_SW_RST             14
0022 #define MT8195_TOPRGU_CAMSYS_SW_RST            15
0023 #define MT8195_TOPRGU_EDPTX_SW_RST             16
0024 #define MT8195_TOPRGU_ADSPSYS_SW_RST           21
0025 #define MT8195_TOPRGU_DPTX_SW_RST              22
0026 #define MT8195_TOPRGU_SPMI_MST_SW_RST          23
0027
0028 #define MT8195_TOPRGU_SW_RST_NUM               16
0029
0030 /* INFRA resets */
0031 #define MT8195_INFRA_RST0_THERM_CTRL_SWRST     0
0032 #define MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST 1
0033 #define MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST 2
0034
0035 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */