dt-bindings/reset/mt8192-resets.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2020 MediaTek Inc.
0004  * Author: Yong Liang <yong.liang@mediatek.com>
0005  */
0006
0007 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192
0008 #define _DT_BINDINGS_RESET_CONTROLLER_MT8192
0009
0010 /* TOPRGU resets */
0011 #define MT8192_TOPRGU_MM_SW_RST                 1
0012 #define MT8192_TOPRGU_MFG_SW_RST                2
0013 #define MT8192_TOPRGU_VENC_SW_RST               3
0014 #define MT8192_TOPRGU_VDEC_SW_RST               4
0015 #define MT8192_TOPRGU_IMG_SW_RST                5
0016 #define MT8192_TOPRGU_MD_SW_RST                 7
0017 #define MT8192_TOPRGU_CONN_SW_RST               9
0018 #define MT8192_TOPRGU_CONN_MCU_SW_RST           12
0019 #define MT8192_TOPRGU_IPU0_SW_RST               14
0020 #define MT8192_TOPRGU_IPU1_SW_RST               15
0021 #define MT8192_TOPRGU_AUDIO_SW_RST              17
0022 #define MT8192_TOPRGU_CAMSYS_SW_RST             18
0023 #define MT8192_TOPRGU_MJC_SW_RST                19
0024 #define MT8192_TOPRGU_C2K_S2_SW_RST             20
0025 #define MT8192_TOPRGU_C2K_SW_RST                21
0026 #define MT8192_TOPRGU_PERI_SW_RST               22
0027 #define MT8192_TOPRGU_PERI_AO_SW_RST            23
0028
0029 #define MT8192_TOPRGU_SW_RST_NUM                23
0030
0031 /* MMSYS resets */
0032 #define MT8192_MMSYS_SW0_RST_B_DISP_DSI0            15
0033
0034 /* INFRA resets */
0035 #define MT8192_INFRA_RST0_THERM_CTRL_SWRST      0
0036 #define MT8192_INFRA_RST2_PEXTP_PHY_SWRST       1
0037 #define MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST  2
0038 #define MT8192_INFRA_RST4_PCIE_TOP_SWRST        3
0039 #define MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST  4
0040
0041 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */