dt-bindings/reset/mt8186-resets.h

0001 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
0002 /*
0003  * Copyright (c) 2022 MediaTek Inc.
0004  * Author: Runyang Chen <runyang.chen@mediatek.com>
0005  */
0006
0007 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8186
0008 #define _DT_BINDINGS_RESET_CONTROLLER_MT8186
0009
0010 /* TOPRGU resets */
0011 #define MT8186_TOPRGU_INFRA_SW_RST              0
0012 #define MT8186_TOPRGU_MM_SW_RST                 1
0013 #define MT8186_TOPRGU_MFG_SW_RST                2
0014 #define MT8186_TOPRGU_VENC_SW_RST               3
0015 #define MT8186_TOPRGU_VDEC_SW_RST               4
0016 #define MT8186_TOPRGU_IMG_SW_RST                5
0017 #define MT8186_TOPRGU_DDR_SW_RST                6
0018 #define MT8186_TOPRGU_INFRA_AO_SW_RST               8
0019 #define MT8186_TOPRGU_CONNSYS_SW_RST                9
0020 #define MT8186_TOPRGU_APMIXED_SW_RST                10
0021 #define MT8186_TOPRGU_PWRAP_SW_RST              11
0022 #define MT8186_TOPRGU_CONN_MCU_SW_RST               12
0023 #define MT8186_TOPRGU_IPNNA_SW_RST              13
0024 #define MT8186_TOPRGU_WPE_SW_RST                14
0025 #define MT8186_TOPRGU_ADSP_SW_RST               15
0026 #define MT8186_TOPRGU_AUDIO_SW_RST              17
0027 #define MT8186_TOPRGU_CAM_MAIN_SW_RST               18
0028 #define MT8186_TOPRGU_CAM_RAWA_SW_RST               19
0029 #define MT8186_TOPRGU_CAM_RAWB_SW_RST               20
0030 #define MT8186_TOPRGU_IPE_SW_RST                21
0031 #define MT8186_TOPRGU_IMG2_SW_RST               22
0032 #define MT8186_TOPRGU_SW_RST_NUM                23
0033
0034 /* MMSYS resets */
0035 #define MT8186_MMSYS_SW0_RST_B_DISP_DSI0            19
0036
0037 /* INFRA resets */
0038 #define MT8186_INFRA_THERMAL_CTRL_RST           0
0039 #define MT8186_INFRA_PTP_CTRL_RST               1
0040
0041 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8186 */