dt-bindings/reset/mt8173-resets.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2014 MediaTek Inc.
0004  * Author: Flora Fu, MediaTek
0005  */
0006
0007 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8173
0008 #define _DT_BINDINGS_RESET_CONTROLLER_MT8173
0009
0010 /* INFRACFG resets */
0011 #define MT8173_INFRA_EMI_REG_RST        0
0012 #define MT8173_INFRA_DRAMC0_A0_RST      1
0013 #define MT8173_INFRA_APCIRQ_EINT_RST    3
0014 #define MT8173_INFRA_APXGPT_RST         4
0015 #define MT8173_INFRA_SCPSYS_RST         5
0016 #define MT8173_INFRA_KP_RST             6
0017 #define MT8173_INFRA_PMIC_WRAP_RST      7
0018 #define MT8173_INFRA_MPIP_RST           8
0019 #define MT8173_INFRA_CEC_RST            9
0020 #define MT8173_INFRA_EMI_RST            32
0021 #define MT8173_INFRA_DRAMC0_RST         34
0022 #define MT8173_INFRA_APMIXEDSYS_RST     35
0023 #define MT8173_INFRA_MIPI_DSI_RST       36
0024 #define MT8173_INFRA_TRNG_RST           37
0025 #define MT8173_INFRA_SYSIRQ_RST         38
0026 #define MT8173_INFRA_MIPI_CSI_RST       39
0027 #define MT8173_INFRA_GCE_FAXI_RST       40
0028 #define MT8173_INFRA_MMIOMMURST         47
0029
0030 /* MMSYS resets */
0031 #define MT8173_MMSYS_SW0_RST_B_DISP_DSI0    25
0032
0033 /*  PERICFG resets */
0034 #define MT8173_PERI_UART0_SW_RST        0
0035 #define MT8173_PERI_UART1_SW_RST        1
0036 #define MT8173_PERI_UART2_SW_RST        2
0037 #define MT8173_PERI_UART3_SW_RST        3
0038 #define MT8173_PERI_IRRX_SW_RST         4
0039 #define MT8173_PERI_PWM_SW_RST          8
0040 #define MT8173_PERI_AUXADC_SW_RST       10
0041 #define MT8173_PERI_DMA_SW_RST          11
0042 #define MT8173_PERI_I2C6_SW_RST         13
0043 #define MT8173_PERI_NFI_SW_RST          14
0044 #define MT8173_PERI_THERM_SW_RST        16
0045 #define MT8173_PERI_MSDC2_SW_RST        17
0046 #define MT8173_PERI_MSDC3_SW_RST        18
0047 #define MT8173_PERI_MSDC0_SW_RST        19
0048 #define MT8173_PERI_MSDC1_SW_RST        20
0049 #define MT8173_PERI_I2C0_SW_RST         22
0050 #define MT8173_PERI_I2C1_SW_RST         23
0051 #define MT8173_PERI_I2C2_SW_RST         24
0052 #define MT8173_PERI_I2C3_SW_RST         25
0053 #define MT8173_PERI_I2C4_SW_RST         26
0054 #define MT8173_PERI_HDMI_SW_RST         29
0055 #define MT8173_PERI_SPI0_SW_RST         33
0056
0057 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8173 */