dt-bindings/reset/mt7986-resets.h

0001 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
0002 /*
0003  * Copyright (c) 2022 MediaTek Inc.
0004  * Author: Sam Shih <sam.shih@mediatek.com>
0005  */
0006
0007 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7986
0008 #define _DT_BINDINGS_RESET_CONTROLLER_MT7986
0009
0010 /* INFRACFG resets */
0011 #define MT7986_INFRACFG_PEXTP_MAC_SW_RST    6
0012 #define MT7986_INFRACFG_SSUSB_SW_RST        7
0013 #define MT7986_INFRACFG_EIP97_SW_RST        8
0014 #define MT7986_INFRACFG_AUDIO_SW_RST        13
0015 #define MT7986_INFRACFG_CQ_DMA_SW_RST       14
0016
0017 #define MT7986_INFRACFG_TRNG_SW_RST     17
0018 #define MT7986_INFRACFG_AP_DMA_SW_RST       32
0019 #define MT7986_INFRACFG_I2C_SW_RST      33
0020 #define MT7986_INFRACFG_NFI_SW_RST      34
0021 #define MT7986_INFRACFG_SPI0_SW_RST     35
0022 #define MT7986_INFRACFG_SPI1_SW_RST     36
0023 #define MT7986_INFRACFG_UART0_SW_RST        37
0024 #define MT7986_INFRACFG_UART1_SW_RST        38
0025 #define MT7986_INFRACFG_UART2_SW_RST        39
0026 #define MT7986_INFRACFG_AUXADC_SW_RST       43
0027
0028 #define MT7986_INFRACFG_APXGPT_SW_RST       66
0029 #define MT7986_INFRACFG_PWM_SW_RST      68
0030
0031 #define MT7986_INFRACFG_SW_RST_NUM      69
0032
0033 /* TOPRGU resets */
0034 #define MT7986_TOPRGU_APMIXEDSYS_SW_RST     0
0035 #define MT7986_TOPRGU_SGMII0_SW_RST     1
0036 #define MT7986_TOPRGU_SGMII1_SW_RST     2
0037 #define MT7986_TOPRGU_INFRA_SW_RST      3
0038 #define MT7986_TOPRGU_U2PHY_SW_RST      5
0039 #define MT7986_TOPRGU_PCIE_SW_RST       6
0040 #define MT7986_TOPRGU_SSUSB_SW_RST      7
0041 #define MT7986_TOPRGU_ETHDMA_SW_RST     20
0042 #define MT7986_TOPRGU_CONSYS_SW_RST     23
0043
0044 #define MT7986_TOPRGU_SW_RST_NUM        24
0045
0046 /* ETHSYS Subsystem resets */
0047 #define MT7986_ETHSYS_FE_SW_RST         6
0048 #define MT7986_ETHSYS_PMTR_SW_RST       8
0049 #define MT7986_ETHSYS_GMAC_SW_RST       23
0050 #define MT7986_ETHSYS_PPE0_SW_RST       30
0051 #define MT7986_ETHSYS_PPE1_SW_RST       31
0052
0053 #define MT7986_ETHSYS_SW_RST_NUM        32
0054
0055 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT7986 */