dt-bindings/reset/mt7629-resets.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) 2019 MediaTek Inc.
0004  */
0005
0006 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7629
0007 #define _DT_BINDINGS_RESET_CONTROLLER_MT7629
0008
0009 /* INFRACFG resets */
0010 #define MT7629_INFRA_EMI_MPU_RST        0
0011 #define MT7629_INFRA_UART5_RST          2
0012 #define MT7629_INFRA_CIRQ_EINT_RST      3
0013 #define MT7629_INFRA_APXGPT_RST         4
0014 #define MT7629_INFRA_SCPSYS_RST         5
0015 #define MT7629_INFRA_KP_RST         6
0016 #define MT7629_INFRA_SPI1_RST           7
0017 #define MT7629_INFRA_SPI4_RST           8
0018 #define MT7629_INFRA_SYSTIMER_RST       9
0019 #define MT7629_INFRA_IRRX_RST           10
0020 #define MT7629_INFRA_AO_BUS_RST         16
0021 #define MT7629_INFRA_EMI_RST            32
0022 #define MT7629_INFRA_APMIXED_RST        35
0023 #define MT7629_INFRA_MIPI_RST           36
0024 #define MT7629_INFRA_TRNG_RST           37
0025 #define MT7629_INFRA_SYSCIRQ_RST        38
0026 #define MT7629_INFRA_MIPI_CSI_RST       39
0027 #define MT7629_INFRA_GCE_FAXI_RST       40
0028 #define MT7629_INFRA_I2C_SRAM_RST       41
0029 #define MT7629_INFRA_IOMMU_RST          47
0030
0031 /* PERICFG resets */
0032 #define MT7629_PERI_UART0_SW_RST        0
0033 #define MT7629_PERI_UART1_SW_RST        1
0034 #define MT7629_PERI_UART2_SW_RST        2
0035 #define MT7629_PERI_BTIF_SW_RST         6
0036 #define MT7629_PERI_PWN_SW_RST          8
0037 #define MT7629_PERI_DMA_SW_RST          11
0038 #define MT7629_PERI_NFI_SW_RST          14
0039 #define MT7629_PERI_I2C0_SW_RST         22
0040 #define MT7629_PERI_SPI0_SW_RST         33
0041 #define MT7629_PERI_SPI1_SW_RST         34
0042 #define MT7629_PERI_FLASHIF_SW_RST      36
0043
0044 /* PCIe Subsystem resets */
0045 #define MT7629_PCIE1_CORE_RST           19
0046 #define MT7629_PCIE1_MMIO_RST           20
0047 #define MT7629_PCIE1_HRST           21
0048 #define MT7629_PCIE1_USER_RST           22
0049 #define MT7629_PCIE1_PIPE_RST           23
0050 #define MT7629_PCIE0_CORE_RST           27
0051 #define MT7629_PCIE0_MMIO_RST           28
0052 #define MT7629_PCIE0_HRST           29
0053 #define MT7629_PCIE0_USER_RST           30
0054 #define MT7629_PCIE0_PIPE_RST           31
0055
0056 /* SSUSB Subsystem resets */
0057 #define MT7629_SSUSB_PHY_PWR_RST        3
0058 #define MT7629_SSUSB_MAC_PWR_RST        4
0059
0060 /* ETH Subsystem resets */
0061 #define MT7629_ETHSYS_SYS_RST           0
0062 #define MT7629_ETHSYS_MCM_RST           2
0063 #define MT7629_ETHSYS_HSDMA_RST         5
0064 #define MT7629_ETHSYS_FE_RST            6
0065 #define MT7629_ETHSYS_ESW_RST           16
0066 #define MT7629_ETHSYS_GMAC_RST          23
0067 #define MT7629_ETHSYS_EPHY_RST          24
0068 #define MT7629_ETHSYS_CRYPTO_RST        29
0069 #define MT7629_ETHSYS_PPE_RST           31
0070
0071 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT7629 */