dt-bindings/reset/mt7622-reset.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2017 MediaTek Inc.
0004  * Author: Sean Wang <sean.wang@mediatek.com>
0005  */
0006
0007 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7622
0008 #define _DT_BINDINGS_RESET_CONTROLLER_MT7622
0009
0010 /* INFRACFG resets */
0011 #define MT7622_INFRA_EMI_REG_RST        0
0012 #define MT7622_INFRA_DRAMC0_A0_RST      1
0013 #define MT7622_INFRA_APCIRQ_EINT_RST        3
0014 #define MT7622_INFRA_APXGPT_RST         4
0015 #define MT7622_INFRA_SCPSYS_RST         5
0016 #define MT7622_INFRA_PMIC_WRAP_RST      7
0017 #define MT7622_INFRA_IRRX_RST           9
0018 #define MT7622_INFRA_EMI_RST            16
0019 #define MT7622_INFRA_WED0_RST           17
0020 #define MT7622_INFRA_DRAMC_RST          18
0021 #define MT7622_INFRA_CCI_INTF_RST       19
0022 #define MT7622_INFRA_TRNG_RST           21
0023 #define MT7622_INFRA_SYSIRQ_RST         22
0024 #define MT7622_INFRA_WED1_RST           25
0025
0026 /* PERICFG Subsystem resets */
0027 #define MT7622_PERI_UART0_SW_RST        0
0028 #define MT7622_PERI_UART1_SW_RST        1
0029 #define MT7622_PERI_UART2_SW_RST        2
0030 #define MT7622_PERI_UART3_SW_RST        3
0031 #define MT7622_PERI_UART4_SW_RST        4
0032 #define MT7622_PERI_BTIF_SW_RST         6
0033 #define MT7622_PERI_PWM_SW_RST          8
0034 #define MT7622_PERI_AUXADC_SW_RST       10
0035 #define MT7622_PERI_DMA_SW_RST          11
0036 #define MT7622_PERI_IRTX_SW_RST         13
0037 #define MT7622_PERI_NFI_SW_RST          14
0038 #define MT7622_PERI_THERM_SW_RST        16
0039 #define MT7622_PERI_MSDC0_SW_RST        19
0040 #define MT7622_PERI_MSDC1_SW_RST        20
0041 #define MT7622_PERI_I2C0_SW_RST         22
0042 #define MT7622_PERI_I2C1_SW_RST         23
0043 #define MT7622_PERI_I2C2_SW_RST         24
0044 #define MT7622_PERI_SPI0_SW_RST         33
0045 #define MT7622_PERI_SPI1_SW_RST         34
0046 #define MT7622_PERI_FLASHIF_SW_RST      36
0047
0048 /* TOPRGU resets */
0049 #define MT7622_TOPRGU_INFRA_RST         0
0050 #define MT7622_TOPRGU_ETHDMA_RST        1
0051 #define MT7622_TOPRGU_DDRPHY_RST        6
0052 #define MT7622_TOPRGU_INFRA_AO_RST      8
0053 #define MT7622_TOPRGU_CONN_RST          9
0054 #define MT7622_TOPRGU_APMIXED_RST       10
0055 #define MT7622_TOPRGU_CONN_MCU_RST      12
0056
0057 /* PCIe/SATA Subsystem resets */
0058 #define MT7622_SATA_PHY_REG_RST         12
0059 #define MT7622_SATA_PHY_SW_RST          13
0060 #define MT7622_SATA_AXI_BUS_RST         15
0061 #define MT7622_PCIE1_CORE_RST           19
0062 #define MT7622_PCIE1_MMIO_RST           20
0063 #define MT7622_PCIE1_HRST           21
0064 #define MT7622_PCIE1_USER_RST           22
0065 #define MT7622_PCIE1_PIPE_RST           23
0066 #define MT7622_PCIE0_CORE_RST           27
0067 #define MT7622_PCIE0_MMIO_RST           28
0068 #define MT7622_PCIE0_HRST           29
0069 #define MT7622_PCIE0_USER_RST           30
0070 #define MT7622_PCIE0_PIPE_RST           31
0071
0072 /* SSUSB Subsystem resets */
0073 #define MT7622_SSUSB_PHY_PWR_RST        3
0074 #define MT7622_SSUSB_MAC_PWR_RST        4
0075
0076 /* ETHSYS Subsystem resets */
0077 #define MT7622_ETHSYS_SYS_RST           0
0078 #define MT7622_ETHSYS_MCM_RST           2
0079 #define MT7622_ETHSYS_HSDMA_RST         5
0080 #define MT7622_ETHSYS_FE_RST            6
0081 #define MT7622_ETHSYS_GMAC_RST          23
0082 #define MT7622_ETHSYS_EPHY_RST          24
0083 #define MT7622_ETHSYS_CRYPTO_RST        29
0084 #define MT7622_ETHSYS_PPE_RST           31
0085
0086 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT7622 */