dt-bindings/reset/mt2701-resets.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2015 MediaTek, Shunli Wang <shunli.wang@mediatek.com>
0004  */
0005
0006 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2701
0007 #define _DT_BINDINGS_RESET_CONTROLLER_MT2701
0008
0009 /* INFRACFG resets */
0010 #define MT2701_INFRA_EMI_REG_RST        0
0011 #define MT2701_INFRA_DRAMC0_A0_RST      1
0012 #define MT2701_INFRA_FHCTL_RST          2
0013 #define MT2701_INFRA_APCIRQ_EINT_RST        3
0014 #define MT2701_INFRA_APXGPT_RST         4
0015 #define MT2701_INFRA_SCPSYS_RST         5
0016 #define MT2701_INFRA_KP_RST         6
0017 #define MT2701_INFRA_PMIC_WRAP_RST      7
0018 #define MT2701_INFRA_MIPI_RST           8
0019 #define MT2701_INFRA_IRRX_RST           9
0020 #define MT2701_INFRA_CEC_RST            10
0021 #define MT2701_INFRA_EMI_RST            32
0022 #define MT2701_INFRA_DRAMC0_RST         34
0023 #define MT2701_INFRA_TRNG_RST           37
0024 #define MT2701_INFRA_SYSIRQ_RST         38
0025
0026 /*  PERICFG resets */
0027 #define MT2701_PERI_UART0_SW_RST        0
0028 #define MT2701_PERI_UART1_SW_RST        1
0029 #define MT2701_PERI_UART2_SW_RST        2
0030 #define MT2701_PERI_UART3_SW_RST        3
0031 #define MT2701_PERI_GCPU_SW_RST         5
0032 #define MT2701_PERI_BTIF_SW_RST         6
0033 #define MT2701_PERI_PWM_SW_RST          8
0034 #define MT2701_PERI_AUXADC_SW_RST       10
0035 #define MT2701_PERI_DMA_SW_RST          11
0036 #define MT2701_PERI_NFI_SW_RST          14
0037 #define MT2701_PERI_NLI_SW_RST          15
0038 #define MT2701_PERI_THERM_SW_RST        16
0039 #define MT2701_PERI_MSDC2_SW_RST        17
0040 #define MT2701_PERI_MSDC0_SW_RST        19
0041 #define MT2701_PERI_MSDC1_SW_RST        20
0042 #define MT2701_PERI_I2C0_SW_RST         22
0043 #define MT2701_PERI_I2C1_SW_RST         23
0044 #define MT2701_PERI_I2C2_SW_RST         24
0045 #define MT2701_PERI_I2C3_SW_RST         25
0046 #define MT2701_PERI_USB_SW_RST          28
0047 #define MT2701_PERI_ETH_SW_RST          29
0048 #define MT2701_PERI_SPI0_SW_RST         33
0049
0050 /* TOPRGU resets */
0051 #define MT2701_TOPRGU_INFRA_RST         0
0052 #define MT2701_TOPRGU_MM_RST            1
0053 #define MT2701_TOPRGU_MFG_RST           2
0054 #define MT2701_TOPRGU_ETHDMA_RST        3
0055 #define MT2701_TOPRGU_VDEC_RST          4
0056 #define MT2701_TOPRGU_VENC_IMG_RST      5
0057 #define MT2701_TOPRGU_DDRPHY_RST        6
0058 #define MT2701_TOPRGU_MD_RST            7
0059 #define MT2701_TOPRGU_INFRA_AO_RST      8
0060 #define MT2701_TOPRGU_CONN_RST          9
0061 #define MT2701_TOPRGU_APMIXED_RST       10
0062 #define MT2701_TOPRGU_HIFSYS_RST        11
0063 #define MT2701_TOPRGU_CONN_MCU_RST      12
0064 #define MT2701_TOPRGU_BDP_DISP_RST      13
0065
0066 /* HIFSYS resets */
0067 #define MT2701_HIFSYS_UHOST0_RST        3
0068 #define MT2701_HIFSYS_UHOST1_RST        4
0069 #define MT2701_HIFSYS_UPHY0_RST         21
0070 #define MT2701_HIFSYS_UPHY1_RST         22
0071 #define MT2701_HIFSYS_PCIE0_RST         24
0072 #define MT2701_HIFSYS_PCIE1_RST         25
0073 #define MT2701_HIFSYS_PCIE2_RST         26
0074
0075 /* ETHSYS resets */
0076 #define MT2701_ETHSYS_SYS_RST           0
0077 #define MT2701_ETHSYS_MCM_RST           2
0078 #define MT2701_ETHSYS_FE_RST            6
0079 #define MT2701_ETHSYS_GMAC_RST          23
0080 #define MT2701_ETHSYS_PPE_RST           31
0081
0082 /* G3DSYS resets */
0083 #define MT2701_G3DSYS_CORE_RST          0
0084
0085 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */