dt-bindings/reset/k210-rst.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * Copyright (C) 2019 Sean Anderson <seanga2@gmail.com>
0004  * Copyright (c) 2020 Western Digital Corporation or its affiliates.
0005  */
0006 #ifndef RESET_K210_SYSCTL_H
0007 #define RESET_K210_SYSCTL_H
0008
0009 /*
0010  * Kendryte K210 SoC system controller K210_SYSCTL_SOFT_RESET register bits.
0011  * Taken from Kendryte SDK (kendryte-standalone-sdk).
0012  */
0013 #define K210_RST_ROM    0
0014 #define K210_RST_DMA    1
0015 #define K210_RST_AI 2
0016 #define K210_RST_DVP    3
0017 #define K210_RST_FFT    4
0018 #define K210_RST_GPIO   5
0019 #define K210_RST_SPI0   6
0020 #define K210_RST_SPI1   7
0021 #define K210_RST_SPI2   8
0022 #define K210_RST_SPI3   9
0023 #define K210_RST_I2S0   10
0024 #define K210_RST_I2S1   11
0025 #define K210_RST_I2S2   12
0026 #define K210_RST_I2C0   13
0027 #define K210_RST_I2C1   14
0028 #define K210_RST_I2C2   15
0029 #define K210_RST_UART1  16
0030 #define K210_RST_UART2  17
0031 #define K210_RST_UART3  18
0032 #define K210_RST_AES    19
0033 #define K210_RST_FPIOA  20
0034 #define K210_RST_TIMER0 21
0035 #define K210_RST_TIMER1 22
0036 #define K210_RST_TIMER2 23
0037 #define K210_RST_WDT0   24
0038 #define K210_RST_WDT1   25
0039 #define K210_RST_SHA    26
0040 #define K210_RST_RTC    29
0041
0042 #endif /* RESET_K210_SYSCTL_H */