dt-bindings/reset/imx8ulp-pcc-reset.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright 2021 NXP
0004  */
0005
0006 #ifndef DT_BINDING_PCC_RESET_IMX8ULP_H
0007 #define DT_BINDING_PCC_RESET_IMX8ULP_H
0008
0009 /* PCC3 */
0010 #define PCC3_WDOG3_SWRST    0
0011 #define PCC3_WDOG4_SWRST    1
0012 #define PCC3_LPIT1_SWRST    2
0013 #define PCC3_TPM4_SWRST     3
0014 #define PCC3_TPM5_SWRST     4
0015 #define PCC3_FLEXIO1_SWRST  5
0016 #define PCC3_I3C2_SWRST     6
0017 #define PCC3_LPI2C4_SWRST   7
0018 #define PCC3_LPI2C5_SWRST   8
0019 #define PCC3_LPUART4_SWRST  9
0020 #define PCC3_LPUART5_SWRST  10
0021 #define PCC3_LPSPI4_SWRST   11
0022 #define PCC3_LPSPI5_SWRST   12
0023
0024 /* PCC4 */
0025 #define PCC4_FLEXSPI2_SWRST 0
0026 #define PCC4_TPM6_SWRST     1
0027 #define PCC4_TPM7_SWRST     2
0028 #define PCC4_LPI2C6_SWRST   3
0029 #define PCC4_LPI2C7_SWRST   4
0030 #define PCC4_LPUART6_SWRST  5
0031 #define PCC4_LPUART7_SWRST  6
0032 #define PCC4_SAI4_SWRST     7
0033 #define PCC4_SAI5_SWRST     8
0034 #define PCC4_USDHC0_SWRST   9
0035 #define PCC4_USDHC1_SWRST   10
0036 #define PCC4_USDHC2_SWRST   11
0037 #define PCC4_USB0_SWRST     12
0038 #define PCC4_USB0_PHY_SWRST 13
0039 #define PCC4_USB1_SWRST     14
0040 #define PCC4_USB1_PHY_SWRST 15
0041 #define PCC4_ENET_SWRST     16
0042
0043 /* PCC5 */
0044 #define PCC5_TPM8_SWRST     0
0045 #define PCC5_SAI6_SWRST     1
0046 #define PCC5_SAI7_SWRST     2
0047 #define PCC5_SPDIF_SWRST    3
0048 #define PCC5_ISI_SWRST      4
0049 #define PCC5_CSI_REGS_SWRST 5
0050 #define PCC5_CSI_SWRST      6
0051 #define PCC5_DSI_SWRST      7
0052 #define PCC5_WDOG5_SWRST    8
0053 #define PCC5_EPDC_SWRST     9
0054 #define PCC5_PXP_SWRST      10
0055 #define PCC5_GPU2D_SWRST    11
0056 #define PCC5_GPU3D_SWRST    12
0057 #define PCC5_DC_NANO_SWRST  13
0058
0059 #endif /*DT_BINDING_RESET_IMX8ULP_H */