dt-bindings/reset/imx8mq-reset.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) 2018 Zodiac Inflight Innovations
0004  *
0005  * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
0006  */
0007
0008 #ifndef DT_BINDING_RESET_IMX8MQ_H
0009 #define DT_BINDING_RESET_IMX8MQ_H
0010
0011 #define IMX8MQ_RESET_A53_CORE_POR_RESET0    0
0012 #define IMX8MQ_RESET_A53_CORE_POR_RESET1    1
0013 #define IMX8MQ_RESET_A53_CORE_POR_RESET2    2
0014 #define IMX8MQ_RESET_A53_CORE_POR_RESET3    3
0015 #define IMX8MQ_RESET_A53_CORE_RESET0        4
0016 #define IMX8MQ_RESET_A53_CORE_RESET1        5
0017 #define IMX8MQ_RESET_A53_CORE_RESET2        6
0018 #define IMX8MQ_RESET_A53_CORE_RESET3        7
0019 #define IMX8MQ_RESET_A53_DBG_RESET0     8
0020 #define IMX8MQ_RESET_A53_DBG_RESET1     9
0021 #define IMX8MQ_RESET_A53_DBG_RESET2     10
0022 #define IMX8MQ_RESET_A53_DBG_RESET3     11
0023 #define IMX8MQ_RESET_A53_ETM_RESET0     12
0024 #define IMX8MQ_RESET_A53_ETM_RESET1     13
0025 #define IMX8MQ_RESET_A53_ETM_RESET2     14
0026 #define IMX8MQ_RESET_A53_ETM_RESET3     15
0027 #define IMX8MQ_RESET_A53_SOC_DBG_RESET      16
0028 #define IMX8MQ_RESET_A53_L2RESET        17
0029 #define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST    18
0030 #define IMX8MQ_RESET_OTG1_PHY_RESET     19
0031 #define IMX8MQ_RESET_OTG2_PHY_RESET     20  /* i.MX8MN does NOT support */
0032 #define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N  21  /* i.MX8MN does NOT support */
0033 #define IMX8MQ_RESET_MIPI_DSI_RESET_N       22  /* i.MX8MN does NOT support */
0034 #define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N   23  /* i.MX8MN does NOT support */
0035 #define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N   24  /* i.MX8MN does NOT support */
0036 #define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N  25  /* i.MX8MN does NOT support */
0037 #define IMX8MQ_RESET_PCIEPHY            26  /* i.MX8MN does NOT support */
0038 #define IMX8MQ_RESET_PCIEPHY_PERST      27  /* i.MX8MN does NOT support */
0039 #define IMX8MQ_RESET_PCIE_CTRL_APPS_EN      28  /* i.MX8MN does NOT support */
0040 #define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29  /* i.MX8MN does NOT support */
0041 #define IMX8MQ_RESET_HDMI_PHY_APB_RESET     30  /* i.MX8MM/i.MX8MN does NOT support */
0042 #define IMX8MQ_RESET_DISP_RESET         31
0043 #define IMX8MQ_RESET_GPU_RESET          32
0044 #define IMX8MQ_RESET_VPU_RESET          33  /* i.MX8MN does NOT support */
0045 #define IMX8MQ_RESET_PCIEPHY2           34  /* i.MX8MM/i.MX8MN does NOT support */
0046 #define IMX8MQ_RESET_PCIEPHY2_PERST     35  /* i.MX8MM/i.MX8MN does NOT support */
0047 #define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN     36  /* i.MX8MM/i.MX8MN does NOT support */
0048 #define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF    37  /* i.MX8MM/i.MX8MN does NOT support */
0049 #define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET   38  /* i.MX8MM/i.MX8MN does NOT support */
0050 #define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET    39  /* i.MX8MM/i.MX8MN does NOT support */
0051 #define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET    40  /* i.MX8MM/i.MX8MN does NOT support */
0052 #define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET   41  /* i.MX8MM/i.MX8MN does NOT support */
0053 #define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET    42  /* i.MX8MM/i.MX8MN does NOT support */
0054 #define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET    43  /* i.MX8MM/i.MX8MN does NOT support */
0055 #define IMX8MQ_RESET_DDRC1_PRST         44  /* i.MX8MN does NOT support */
0056 #define IMX8MQ_RESET_DDRC1_CORE_RESET       45  /* i.MX8MN does NOT support */
0057 #define IMX8MQ_RESET_DDRC1_PHY_RESET        46  /* i.MX8MN does NOT support */
0058 #define IMX8MQ_RESET_DDRC2_PRST         47  /* i.MX8MM/i.MX8MN does NOT support */
0059 #define IMX8MQ_RESET_DDRC2_CORE_RESET       48  /* i.MX8MM/i.MX8MN does NOT support */
0060 #define IMX8MQ_RESET_DDRC2_PHY_RESET        49  /* i.MX8MM/i.MX8MN does NOT support */
0061 #define IMX8MQ_RESET_SW_M4C_RST         50
0062 #define IMX8MQ_RESET_SW_M4P_RST         51
0063 #define IMX8MQ_RESET_M4_ENABLE          52
0064
0065 #define IMX8MQ_RESET_NUM            53
0066
0067 #endif