dt-bindings/reset/imx7-reset.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2017 Impinj, Inc.
0004  *
0005  * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
0006  */
0007
0008 #ifndef DT_BINDING_RESET_IMX7_H
0009 #define DT_BINDING_RESET_IMX7_H
0010
0011 #define IMX7_RESET_A7_CORE_POR_RESET0   0
0012 #define IMX7_RESET_A7_CORE_POR_RESET1   1
0013 #define IMX7_RESET_A7_CORE_RESET0   2
0014 #define IMX7_RESET_A7_CORE_RESET1   3
0015 #define IMX7_RESET_A7_DBG_RESET0    4
0016 #define IMX7_RESET_A7_DBG_RESET1    5
0017 #define IMX7_RESET_A7_ETM_RESET0    6
0018 #define IMX7_RESET_A7_ETM_RESET1    7
0019 #define IMX7_RESET_A7_SOC_DBG_RESET 8
0020 #define IMX7_RESET_A7_L2RESET       9
0021 #define IMX7_RESET_SW_M4C_RST       10
0022 #define IMX7_RESET_SW_M4P_RST       11
0023 #define IMX7_RESET_EIM_RST      12
0024 #define IMX7_RESET_HSICPHY_PORT_RST 13
0025 #define IMX7_RESET_USBPHY1_POR      14
0026 #define IMX7_RESET_USBPHY1_PORT_RST 15
0027 #define IMX7_RESET_USBPHY2_POR      16
0028 #define IMX7_RESET_USBPHY2_PORT_RST 17
0029 #define IMX7_RESET_MIPI_PHY_MRST    18
0030 #define IMX7_RESET_MIPI_PHY_SRST    19
0031
0032 /*
0033  * IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN
0034  * and PCIEPHY_G_RST
0035  */
0036 #define IMX7_RESET_PCIEPHY      20
0037 #define IMX7_RESET_PCIEPHY_PERST    21
0038
0039 /*
0040  * IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it
0041  * can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht
0042  * of as one
0043  */
0044 #define IMX7_RESET_PCIE_CTRL_APPS_EN    22
0045 #define IMX7_RESET_DDRC_PRST        23
0046 #define IMX7_RESET_DDRC_CORE_RST    24
0047
0048 #define IMX7_RESET_PCIE_CTRL_APPS_TURNOFF 25
0049
0050 #define IMX7_RESET_NUM          26
0051
0052 #endif
0053