dt-bindings/reset/altr%2Crst-mgr-s10.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2016 Intel Corporation. All rights reserved
0004  * Copyright (C) 2016 Altera Corporation. All rights reserved
0005  *
0006  * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h"
0007  */
0008
0009 #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
0010 #define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
0011
0012 /* MPUMODRST */
0013 #define CPU0_RESET      0
0014 #define CPU1_RESET      1
0015 #define CPU2_RESET      2
0016 #define CPU3_RESET      3
0017
0018 /* PER0MODRST */
0019 #define EMAC0_RESET     32
0020 #define EMAC1_RESET     33
0021 #define EMAC2_RESET     34
0022 #define USB0_RESET      35
0023 #define USB1_RESET      36
0024 #define NAND_RESET      37
0025 /* 38 is empty */
0026 #define SDMMC_RESET     39
0027 #define EMAC0_OCP_RESET     40
0028 #define EMAC1_OCP_RESET     41
0029 #define EMAC2_OCP_RESET     42
0030 #define USB0_OCP_RESET      43
0031 #define USB1_OCP_RESET      44
0032 #define NAND_OCP_RESET      45
0033 /* 46 is empty */
0034 #define SDMMC_OCP_RESET     47
0035 #define DMA_RESET       48
0036 #define SPIM0_RESET     49
0037 #define SPIM1_RESET     50
0038 #define SPIS0_RESET     51
0039 #define SPIS1_RESET     52
0040 #define DMA_OCP_RESET       53
0041 #define EMAC_PTP_RESET      54
0042 /* 55 is empty*/
0043 #define DMAIF0_RESET        56
0044 #define DMAIF1_RESET        57
0045 #define DMAIF2_RESET        58
0046 #define DMAIF3_RESET        59
0047 #define DMAIF4_RESET        60
0048 #define DMAIF5_RESET        61
0049 #define DMAIF6_RESET        62
0050 #define DMAIF7_RESET        63
0051
0052 /* PER1MODRST */
0053 #define WATCHDOG0_RESET     64
0054 #define WATCHDOG1_RESET     65
0055 #define WATCHDOG2_RESET     66
0056 #define WATCHDOG3_RESET     67
0057 #define L4SYSTIMER0_RESET   68
0058 #define L4SYSTIMER1_RESET   69
0059 #define SPTIMER0_RESET      70
0060 #define SPTIMER1_RESET      71
0061 #define I2C0_RESET      72
0062 #define I2C1_RESET      73
0063 #define I2C2_RESET      74
0064 #define I2C3_RESET      75
0065 #define I2C4_RESET      76
0066 /* 77-79 is empty */
0067 #define UART0_RESET     80
0068 #define UART1_RESET     81
0069 /* 82-87 is empty */
0070 #define GPIO0_RESET     88
0071 #define GPIO1_RESET     89
0072
0073 /* BRGMODRST */
0074 #define SOC2FPGA_RESET      96
0075 #define LWHPS2FPGA_RESET    97
0076 #define FPGA2SOC_RESET      98
0077 #define F2SSDRAM0_RESET     99
0078 #define F2SSDRAM1_RESET     100
0079 #define F2SSDRAM2_RESET     101
0080 #define DDRSCH_RESET        102
0081
0082 /* COLDMODRST */
0083 #define CPUPO0_RESET        160
0084 #define CPUPO1_RESET        161
0085 #define CPUPO2_RESET        162
0086 #define CPUPO3_RESET        163
0087 /* 164-167 is empty */
0088 #define L2_RESET        168
0089
0090 /* DBGMODRST */
0091 #define DBG_RESET       224
0092 #define CSDAP_RESET     225
0093
0094 /* TAPMODRST */
0095 #define TAP_RESET       256
0096
0097 #endif