dt-bindings/reset/actions%2Cs500-reset.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * Device Tree binding constants for Actions Semi S500 Reset Management Unit
0004  *
0005  * Copyright (c) 2014 Actions Semi Inc.
0006  * Copyright (c) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
0007  */
0008
0009 #ifndef __DT_BINDINGS_ACTIONS_S500_RESET_H
0010 #define __DT_BINDINGS_ACTIONS_S500_RESET_H
0011
0012 #define RESET_DMAC              0
0013 #define RESET_NORIF             1
0014 #define RESET_DDR               2
0015 #define RESET_NANDC             3
0016 #define RESET_SD0               4
0017 #define RESET_SD1               5
0018 #define RESET_PCM1              6
0019 #define RESET_DE                7
0020 #define RESET_LCD               8
0021 #define RESET_SD2               9
0022 #define RESET_DSI               10
0023 #define RESET_CSI               11
0024 #define RESET_BISP              12
0025 #define RESET_KEY               13
0026 #define RESET_GPIO              14
0027 #define RESET_AUDIO             15
0028 #define RESET_PCM0              16
0029 #define RESET_VDE               17
0030 #define RESET_VCE               18
0031 #define RESET_GPU3D             19
0032 #define RESET_NIC301                20
0033 #define RESET_LENS              21
0034 #define RESET_PERIPHRESET           22
0035 #define RESET_USB2_0                23
0036 #define RESET_TVOUT             24
0037 #define RESET_HDMI              25
0038 #define RESET_HDCP2TX               26
0039 #define RESET_UART6             27
0040 #define RESET_UART0             28
0041 #define RESET_UART1             29
0042 #define RESET_UART2             30
0043 #define RESET_SPI0              31
0044 #define RESET_SPI1              32
0045 #define RESET_SPI2              33
0046 #define RESET_SPI3              34
0047 #define RESET_I2C0              35
0048 #define RESET_I2C1              36
0049 #define RESET_USB3              37
0050 #define RESET_UART3             38
0051 #define RESET_UART4             39
0052 #define RESET_UART5             40
0053 #define RESET_I2C2              41
0054 #define RESET_I2C3              42
0055 #define RESET_ETHERNET              43
0056 #define RESET_CHIPID                44
0057 #define RESET_USB2_1                45
0058 #define RESET_WD0RESET              46
0059 #define RESET_WD1RESET              47
0060 #define RESET_WD2RESET              48
0061 #define RESET_WD3RESET              49
0062 #define RESET_DBG0RESET             50
0063 #define RESET_DBG1RESET             51
0064 #define RESET_DBG2RESET             52
0065 #define RESET_DBG3RESET             53
0066
0067 #endif /* __DT_BINDINGS_ACTIONS_S500_RESET_H */