dt-bindings/net/ti-dp83869.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Device Tree constants for the Texas Instruments DP83869 PHY
0004  *
0005  * Author: Dan Murphy <dmurphy@ti.com>
0006  *
0007  * Copyright:   (C) 2019 Texas Instruments, Inc.
0008  */
0009
0010 #ifndef _DT_BINDINGS_TI_DP83869_H
0011 #define _DT_BINDINGS_TI_DP83869_H
0012
0013 /* PHY CTRL bits */
0014 #define DP83869_PHYCR_FIFO_DEPTH_3_B_NIB    0x00
0015 #define DP83869_PHYCR_FIFO_DEPTH_4_B_NIB    0x01
0016 #define DP83869_PHYCR_FIFO_DEPTH_6_B_NIB    0x02
0017 #define DP83869_PHYCR_FIFO_DEPTH_8_B_NIB    0x03
0018
0019 /* IO_MUX_CFG - Clock output selection */
0020 #define DP83869_CLK_O_SEL_CHN_A_RCLK        0x0
0021 #define DP83869_CLK_O_SEL_CHN_B_RCLK        0x1
0022 #define DP83869_CLK_O_SEL_CHN_C_RCLK        0x2
0023 #define DP83869_CLK_O_SEL_CHN_D_RCLK        0x3
0024 #define DP83869_CLK_O_SEL_CHN_A_RCLK_DIV5   0x4
0025 #define DP83869_CLK_O_SEL_CHN_B_RCLK_DIV5   0x5
0026 #define DP83869_CLK_O_SEL_CHN_C_RCLK_DIV5   0x6
0027 #define DP83869_CLK_O_SEL_CHN_D_RCLK_DIV5   0x7
0028 #define DP83869_CLK_O_SEL_CHN_A_TCLK        0x8
0029 #define DP83869_CLK_O_SEL_CHN_B_TCLK        0x9
0030 #define DP83869_CLK_O_SEL_CHN_C_TCLK        0xa
0031 #define DP83869_CLK_O_SEL_CHN_D_TCLK        0xb
0032 #define DP83869_CLK_O_SEL_REF_CLK       0xc
0033
0034 #define DP83869_RGMII_COPPER_ETHERNET       0x00
0035 #define DP83869_RGMII_1000_BASE         0x01
0036 #define DP83869_RGMII_100_BASE          0x02
0037 #define DP83869_RGMII_SGMII_BRIDGE      0x03
0038 #define DP83869_1000M_MEDIA_CONVERT     0x04
0039 #define DP83869_100M_MEDIA_CONVERT      0x05
0040 #define DP83869_SGMII_COPPER_ETHERNET       0x06
0041
0042 #endif