dt-bindings/net/ti-dp83867.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Device Tree constants for the Texas Instruments DP83867 PHY
0004  *
0005  * Author: Dan Murphy <dmurphy@ti.com>
0006  *
0007  * Copyright:   (C) 2015 Texas Instruments, Inc.
0008  */
0009
0010 #ifndef _DT_BINDINGS_TI_DP83867_H
0011 #define _DT_BINDINGS_TI_DP83867_H
0012
0013 /* PHY CTRL bits */
0014 #define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB    0x00
0015 #define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB    0x01
0016 #define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB    0x02
0017 #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB    0x03
0018
0019 /* RGMIIDCTL internal delay for rx and tx */
0020 #define DP83867_RGMIIDCTL_250_PS    0x0
0021 #define DP83867_RGMIIDCTL_500_PS    0x1
0022 #define DP83867_RGMIIDCTL_750_PS    0x2
0023 #define DP83867_RGMIIDCTL_1_NS      0x3
0024 #define DP83867_RGMIIDCTL_1_25_NS   0x4
0025 #define DP83867_RGMIIDCTL_1_50_NS   0x5
0026 #define DP83867_RGMIIDCTL_1_75_NS   0x6
0027 #define DP83867_RGMIIDCTL_2_00_NS   0x7
0028 #define DP83867_RGMIIDCTL_2_25_NS   0x8
0029 #define DP83867_RGMIIDCTL_2_50_NS   0x9
0030 #define DP83867_RGMIIDCTL_2_75_NS   0xa
0031 #define DP83867_RGMIIDCTL_3_00_NS   0xb
0032 #define DP83867_RGMIIDCTL_3_25_NS   0xc
0033 #define DP83867_RGMIIDCTL_3_50_NS   0xd
0034 #define DP83867_RGMIIDCTL_3_75_NS   0xe
0035 #define DP83867_RGMIIDCTL_4_00_NS   0xf
0036
0037 /* IO_MUX_CFG - Clock output selection */
0038 #define DP83867_CLK_O_SEL_CHN_A_RCLK        0x0
0039 #define DP83867_CLK_O_SEL_CHN_B_RCLK        0x1
0040 #define DP83867_CLK_O_SEL_CHN_C_RCLK        0x2
0041 #define DP83867_CLK_O_SEL_CHN_D_RCLK        0x3
0042 #define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5   0x4
0043 #define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5   0x5
0044 #define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5   0x6
0045 #define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5   0x7
0046 #define DP83867_CLK_O_SEL_CHN_A_TCLK        0x8
0047 #define DP83867_CLK_O_SEL_CHN_B_TCLK        0x9
0048 #define DP83867_CLK_O_SEL_CHN_C_TCLK        0xA
0049 #define DP83867_CLK_O_SEL_CHN_D_TCLK        0xB
0050 #define DP83867_CLK_O_SEL_REF_CLK       0xC
0051 /* Special flag to indicate clock should be off */
0052 #define DP83867_CLK_O_SEL_OFF           0xFFFFFFFF
0053 #endif