0001
0002 #ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H
0003 #define DT_BINDINGS_MEMORY_TEGRA30_MC_H
0004
0005 #define TEGRA_SWGROUP_PTC 0
0006 #define TEGRA_SWGROUP_DC 1
0007 #define TEGRA_SWGROUP_DCB 2
0008 #define TEGRA_SWGROUP_EPP 3
0009 #define TEGRA_SWGROUP_G2 4
0010 #define TEGRA_SWGROUP_MPE 5
0011 #define TEGRA_SWGROUP_VI 6
0012 #define TEGRA_SWGROUP_AFI 7
0013 #define TEGRA_SWGROUP_AVPC 8
0014 #define TEGRA_SWGROUP_NV 9
0015 #define TEGRA_SWGROUP_NV2 10
0016 #define TEGRA_SWGROUP_HDA 11
0017 #define TEGRA_SWGROUP_HC 12
0018 #define TEGRA_SWGROUP_PPCS 13
0019 #define TEGRA_SWGROUP_SATA 14
0020 #define TEGRA_SWGROUP_VDE 15
0021 #define TEGRA_SWGROUP_MPCORELP 16
0022 #define TEGRA_SWGROUP_MPCORE 17
0023 #define TEGRA_SWGROUP_ISP 18
0024
0025 #define TEGRA30_MC_RESET_AFI 0
0026 #define TEGRA30_MC_RESET_AVPC 1
0027 #define TEGRA30_MC_RESET_DC 2
0028 #define TEGRA30_MC_RESET_DCB 3
0029 #define TEGRA30_MC_RESET_EPP 4
0030 #define TEGRA30_MC_RESET_2D 5
0031 #define TEGRA30_MC_RESET_HC 6
0032 #define TEGRA30_MC_RESET_HDA 7
0033 #define TEGRA30_MC_RESET_ISP 8
0034 #define TEGRA30_MC_RESET_MPCORE 9
0035 #define TEGRA30_MC_RESET_MPCORELP 10
0036 #define TEGRA30_MC_RESET_MPE 11
0037 #define TEGRA30_MC_RESET_3D 12
0038 #define TEGRA30_MC_RESET_3D2 13
0039 #define TEGRA30_MC_RESET_PPCS 14
0040 #define TEGRA30_MC_RESET_SATA 15
0041 #define TEGRA30_MC_RESET_VDE 16
0042 #define TEGRA30_MC_RESET_VI 17
0043
0044 #define TEGRA30_MC_PTCR 0
0045 #define TEGRA30_MC_DISPLAY0A 1
0046 #define TEGRA30_MC_DISPLAY0AB 2
0047 #define TEGRA30_MC_DISPLAY0B 3
0048 #define TEGRA30_MC_DISPLAY0BB 4
0049 #define TEGRA30_MC_DISPLAY0C 5
0050 #define TEGRA30_MC_DISPLAY0CB 6
0051 #define TEGRA30_MC_DISPLAY1B 7
0052 #define TEGRA30_MC_DISPLAY1BB 8
0053 #define TEGRA30_MC_EPPUP 9
0054 #define TEGRA30_MC_G2PR 10
0055 #define TEGRA30_MC_G2SR 11
0056 #define TEGRA30_MC_MPEUNIFBR 12
0057 #define TEGRA30_MC_VIRUV 13
0058 #define TEGRA30_MC_AFIR 14
0059 #define TEGRA30_MC_AVPCARM7R 15
0060 #define TEGRA30_MC_DISPLAYHC 16
0061 #define TEGRA30_MC_DISPLAYHCB 17
0062 #define TEGRA30_MC_FDCDRD 18
0063 #define TEGRA30_MC_FDCDRD2 19
0064 #define TEGRA30_MC_G2DR 20
0065 #define TEGRA30_MC_HDAR 21
0066 #define TEGRA30_MC_HOST1XDMAR 22
0067 #define TEGRA30_MC_HOST1XR 23
0068 #define TEGRA30_MC_IDXSRD 24
0069 #define TEGRA30_MC_IDXSRD2 25
0070 #define TEGRA30_MC_MPE_IPRED 26
0071 #define TEGRA30_MC_MPEAMEMRD 27
0072 #define TEGRA30_MC_MPECSRD 28
0073 #define TEGRA30_MC_PPCSAHBDMAR 29
0074 #define TEGRA30_MC_PPCSAHBSLVR 30
0075 #define TEGRA30_MC_SATAR 31
0076 #define TEGRA30_MC_TEXSRD 32
0077 #define TEGRA30_MC_TEXSRD2 33
0078 #define TEGRA30_MC_VDEBSEVR 34
0079 #define TEGRA30_MC_VDEMBER 35
0080 #define TEGRA30_MC_VDEMCER 36
0081 #define TEGRA30_MC_VDETPER 37
0082 #define TEGRA30_MC_MPCORELPR 38
0083 #define TEGRA30_MC_MPCORER 39
0084 #define TEGRA30_MC_EPPU 40
0085 #define TEGRA30_MC_EPPV 41
0086 #define TEGRA30_MC_EPPY 42
0087 #define TEGRA30_MC_MPEUNIFBW 43
0088 #define TEGRA30_MC_VIWSB 44
0089 #define TEGRA30_MC_VIWU 45
0090 #define TEGRA30_MC_VIWV 46
0091 #define TEGRA30_MC_VIWY 47
0092 #define TEGRA30_MC_G2DW 48
0093 #define TEGRA30_MC_AFIW 49
0094 #define TEGRA30_MC_AVPCARM7W 50
0095 #define TEGRA30_MC_FDCDWR 51
0096 #define TEGRA30_MC_FDCDWR2 52
0097 #define TEGRA30_MC_HDAW 53
0098 #define TEGRA30_MC_HOST1XW 54
0099 #define TEGRA30_MC_ISPW 55
0100 #define TEGRA30_MC_MPCORELPW 56
0101 #define TEGRA30_MC_MPCOREW 57
0102 #define TEGRA30_MC_MPECSWR 58
0103 #define TEGRA30_MC_PPCSAHBDMAW 59
0104 #define TEGRA30_MC_PPCSAHBSLVW 60
0105 #define TEGRA30_MC_SATAW 61
0106 #define TEGRA30_MC_VDEBSEVW 62
0107 #define TEGRA30_MC_VDEDBGW 63
0108 #define TEGRA30_MC_VDEMBEW 64
0109 #define TEGRA30_MC_VDETPMW 65
0110
0111 #endif