dt-bindings/memory/tegra234-mc.h

0001 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
0002 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
0003
0004 #ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H
0005 #define DT_BINDINGS_MEMORY_TEGRA234_MC_H
0006
0007 /* special clients */
0008 #define TEGRA234_SID_INVALID        0x00
0009 #define TEGRA234_SID_PASSTHROUGH    0x7f
0010
0011 /* NISO0 stream IDs */
0012 #define TEGRA234_SID_APE    0x02
0013 #define TEGRA234_SID_HDA    0x03
0014 #define TEGRA234_SID_GPCDMA 0x04
0015 #define TEGRA234_SID_MGBE   0x06
0016 #define TEGRA234_SID_PCIE0  0x12
0017 #define TEGRA234_SID_PCIE4  0x13
0018 #define TEGRA234_SID_PCIE5  0x14
0019 #define TEGRA234_SID_PCIE6  0x15
0020 #define TEGRA234_SID_PCIE9  0x1f
0021 #define TEGRA234_SID_MGBE_VF1   0x49
0022 #define TEGRA234_SID_MGBE_VF2   0x4a
0023 #define TEGRA234_SID_MGBE_VF3   0x4b
0024
0025 /* NISO1 stream IDs */
0026 #define TEGRA234_SID_SDMMC4 0x02
0027 #define TEGRA234_SID_PCIE1  0x05
0028 #define TEGRA234_SID_PCIE2  0x06
0029 #define TEGRA234_SID_PCIE3  0x07
0030 #define TEGRA234_SID_PCIE7  0x08
0031 #define TEGRA234_SID_PCIE8  0x09
0032 #define TEGRA234_SID_PCIE10 0x0b
0033 #define TEGRA234_SID_BPMP   0x10
0034 #define TEGRA234_SID_HOST1X 0x27
0035 #define TEGRA234_SID_VIC    0x34
0036
0037 /*
0038  * memory client IDs
0039  */
0040
0041 /* High-definition audio (HDA) read clients */
0042 #define TEGRA234_MEMORY_CLIENT_HDAR 0x15
0043 #define TEGRA234_MEMORY_CLIENT_HOST1XDMAR 0x16
0044 /* PCIE6 read clients */
0045 #define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28
0046 /* PCIE6 write clients */
0047 #define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29
0048 /* PCIE7 read clients */
0049 #define TEGRA234_MEMORY_CLIENT_PCIE7AR 0x2a
0050 /* PCIE7 write clients */
0051 #define TEGRA234_MEMORY_CLIENT_PCIE7AW 0x30
0052 /* PCIE8 read clients */
0053 #define TEGRA234_MEMORY_CLIENT_PCIE8AR 0x32
0054 /* High-definition audio (HDA) write clients */
0055 #define TEGRA234_MEMORY_CLIENT_HDAW 0x35
0056 /* PCIE8 write clients */
0057 #define TEGRA234_MEMORY_CLIENT_PCIE8AW 0x3b
0058 /* PCIE9 read clients */
0059 #define TEGRA234_MEMORY_CLIENT_PCIE9AR 0x3c
0060 /* PCIE6r1 read clients */
0061 #define TEGRA234_MEMORY_CLIENT_PCIE6AR1 0x3d
0062 /* PCIE9 write clients */
0063 #define TEGRA234_MEMORY_CLIENT_PCIE9AW 0x3e
0064 /* PCIE10 read clients */
0065 #define TEGRA234_MEMORY_CLIENT_PCIE10AR 0x3f
0066 /* PCIE10 write clients */
0067 #define TEGRA234_MEMORY_CLIENT_PCIE10AW 0x40
0068 /* PCIE10r1 read clients */
0069 #define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48
0070 /* PCIE7r1 read clients */
0071 #define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49
0072 /* MGBE0 read client */
0073 #define TEGRA234_MEMORY_CLIENT_MGBEARD 0x58
0074 /* MGBEB read client */
0075 #define TEGRA234_MEMORY_CLIENT_MGBEBRD 0x59
0076 /* MGBEC read client */
0077 #define TEGRA234_MEMORY_CLIENT_MGBECRD 0x5a
0078 /* MGBED read client */
0079 #define TEGRA234_MEMORY_CLIENT_MGBEDRD 0x5b
0080 /* MGBE0 write client */
0081 #define TEGRA234_MEMORY_CLIENT_MGBEAWR 0x5c
0082 /* MGBEB write client */
0083 #define TEGRA234_MEMORY_CLIENT_MGBEBWR 0x5f
0084 /* MGBEC write client */
0085 #define TEGRA234_MEMORY_CLIENT_MGBECWR 0x61
0086 /* sdmmcd memory read client */
0087 #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63
0088 /* MGBED write client */
0089 #define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65
0090 /* sdmmcd memory write client */
0091 #define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67
0092 #define TEGRA234_MEMORY_CLIENT_VICSRD 0x6c
0093 #define TEGRA234_MEMORY_CLIENT_VICSWR 0x6d
0094 /* BPMP read client */
0095 #define TEGRA234_MEMORY_CLIENT_BPMPR 0x93
0096 /* BPMP write client */
0097 #define TEGRA234_MEMORY_CLIENT_BPMPW 0x94
0098 /* BPMPDMA read client */
0099 #define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95
0100 /* BPMPDMA write client */
0101 #define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96
0102 /* APEDMA read client */
0103 #define TEGRA234_MEMORY_CLIENT_APEDMAR 0x9f
0104 /* APEDMA write client */
0105 #define TEGRA234_MEMORY_CLIENT_APEDMAW 0xa0
0106 /* PCIE0 read clients */
0107 #define TEGRA234_MEMORY_CLIENT_PCIE0R 0xd8
0108 /* PCIE0 write clients */
0109 #define TEGRA234_MEMORY_CLIENT_PCIE0W 0xd9
0110 /* PCIE1 read clients */
0111 #define TEGRA234_MEMORY_CLIENT_PCIE1R 0xda
0112 /* PCIE1 write clients */
0113 #define TEGRA234_MEMORY_CLIENT_PCIE1W 0xdb
0114 /* PCIE2 read clients */
0115 #define TEGRA234_MEMORY_CLIENT_PCIE2AR 0xdc
0116 /* PCIE2 write clients */
0117 #define TEGRA234_MEMORY_CLIENT_PCIE2AW 0xdd
0118 /* PCIE3 read clients */
0119 #define TEGRA234_MEMORY_CLIENT_PCIE3R 0xde
0120 /* PCIE3 write clients */
0121 #define TEGRA234_MEMORY_CLIENT_PCIE3W 0xdf
0122 /* PCIE4 read clients */
0123 #define TEGRA234_MEMORY_CLIENT_PCIE4R 0xe0
0124 /* PCIE4 write clients */
0125 #define TEGRA234_MEMORY_CLIENT_PCIE4W 0xe1
0126 /* PCIE5 read clients */
0127 #define TEGRA234_MEMORY_CLIENT_PCIE5R 0xe2
0128 /* PCIE5 write clients */
0129 #define TEGRA234_MEMORY_CLIENT_PCIE5W 0xe3
0130 /* PCIE5r1 read clients */
0131 #define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef
0132
0133 #endif