dt-bindings/memory/tegra114-mc.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H
0003 #define DT_BINDINGS_MEMORY_TEGRA114_MC_H
0004
0005 #define TEGRA_SWGROUP_PTC   0
0006 #define TEGRA_SWGROUP_DC    1
0007 #define TEGRA_SWGROUP_DCB   2
0008 #define TEGRA_SWGROUP_EPP   3
0009 #define TEGRA_SWGROUP_G2    4
0010 #define TEGRA_SWGROUP_AVPC  5
0011 #define TEGRA_SWGROUP_NV    6
0012 #define TEGRA_SWGROUP_HDA   7
0013 #define TEGRA_SWGROUP_HC    8
0014 #define TEGRA_SWGROUP_MSENC 9
0015 #define TEGRA_SWGROUP_PPCS  10
0016 #define TEGRA_SWGROUP_VDE   11
0017 #define TEGRA_SWGROUP_MPCORELP  12
0018 #define TEGRA_SWGROUP_MPCORE    13
0019 #define TEGRA_SWGROUP_VI    14
0020 #define TEGRA_SWGROUP_ISP   15
0021 #define TEGRA_SWGROUP_XUSB_HOST 16
0022 #define TEGRA_SWGROUP_XUSB_DEV  17
0023 #define TEGRA_SWGROUP_EMUCIF    18
0024 #define TEGRA_SWGROUP_TSEC  19
0025
0026 #define TEGRA114_MC_RESET_AVPC      0
0027 #define TEGRA114_MC_RESET_DC        1
0028 #define TEGRA114_MC_RESET_DCB       2
0029 #define TEGRA114_MC_RESET_EPP       3
0030 #define TEGRA114_MC_RESET_2D        4
0031 #define TEGRA114_MC_RESET_HC        5
0032 #define TEGRA114_MC_RESET_HDA       6
0033 #define TEGRA114_MC_RESET_ISP       7
0034 #define TEGRA114_MC_RESET_MPCORE    8
0035 #define TEGRA114_MC_RESET_MPCORELP  9
0036 #define TEGRA114_MC_RESET_MPE       10
0037 #define TEGRA114_MC_RESET_3D        11
0038 #define TEGRA114_MC_RESET_3D2       12
0039 #define TEGRA114_MC_RESET_PPCS      13
0040 #define TEGRA114_MC_RESET_VDE       14
0041 #define TEGRA114_MC_RESET_VI        15
0042
0043 #endif