dt-bindings/memory/mt8192-larb-port.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2020 MediaTek Inc.
0004  *
0005  * Author: Chao Hao <chao.hao@mediatek.com>
0006  * Author: Yong Wu <yong.wu@mediatek.com>
0007  */
0008 #ifndef _DT_BINDINGS_MEMORY_MT8192_LARB_PORT_H_
0009 #define _DT_BINDINGS_MEMORY_MT8192_LARB_PORT_H_
0010
0011 #include <dt-bindings/memory/mtk-memory-port.h>
0012
0013 /*
0014  * MM IOMMU supports 16GB dma address.
0015  *
0016  * The address will preassign like this:
0017  *
0018  * modules    dma-address-region    larbs-ports
0019  * disp         0 ~ 4G                   larb0/1
0020  * vcodec      4G ~ 8G                  larb4/5/7
0021  * cam/mdp     8G ~ 12G             larb2/9/11/13/14/16/17/18/19/20
0022  * CCU0    0x4000_0000 ~ 0x43ff_ffff     larb13: port 9/10
0023  * CCU1    0x4400_0000 ~ 0x47ff_ffff     larb14: port 4/5
0024  *
0025  * larb3/6/8/10/12/15 is null.
0026  */
0027
0028 /* larb0 */
0029 #define M4U_PORT_L0_DISP_POSTMASK0      MTK_M4U_ID(0, 0)
0030 #define M4U_PORT_L0_OVL_RDMA0_HDR       MTK_M4U_ID(0, 1)
0031 #define M4U_PORT_L0_OVL_RDMA0           MTK_M4U_ID(0, 2)
0032 #define M4U_PORT_L0_DISP_RDMA0          MTK_M4U_ID(0, 3)
0033 #define M4U_PORT_L0_DISP_WDMA0          MTK_M4U_ID(0, 4)
0034 #define M4U_PORT_L0_DISP_FAKE0          MTK_M4U_ID(0, 5)
0035
0036 /* larb1 */
0037 #define M4U_PORT_L1_OVL_2L_RDMA0_HDR        MTK_M4U_ID(1, 0)
0038 #define M4U_PORT_L1_OVL_2L_RDMA2_HDR        MTK_M4U_ID(1, 1)
0039 #define M4U_PORT_L1_OVL_2L_RDMA0        MTK_M4U_ID(1, 2)
0040 #define M4U_PORT_L1_OVL_2L_RDMA2        MTK_M4U_ID(1, 3)
0041 #define M4U_PORT_L1_DISP_MDP_RDMA4      MTK_M4U_ID(1, 4)
0042 #define M4U_PORT_L1_DISP_RDMA4          MTK_M4U_ID(1, 5)
0043 #define M4U_PORT_L1_DISP_UFBC_WDMA0     MTK_M4U_ID(1, 6)
0044 #define M4U_PORT_L1_DISP_FAKE1          MTK_M4U_ID(1, 7)
0045
0046 /* larb2 */
0047 #define M4U_PORT_L2_MDP_RDMA0           MTK_M4U_ID(2, 0)
0048 #define M4U_PORT_L2_MDP_RDMA1           MTK_M4U_ID(2, 1)
0049 #define M4U_PORT_L2_MDP_WROT0           MTK_M4U_ID(2, 2)
0050 #define M4U_PORT_L2_MDP_WROT1           MTK_M4U_ID(2, 3)
0051 #define M4U_PORT_L2_MDP_DISP_FAKE0      MTK_M4U_ID(2, 4)
0052
0053 /* larb3: null */
0054
0055 /* larb4 */
0056 #define M4U_PORT_L4_VDEC_MC_EXT         MTK_M4U_ID(4, 0)
0057 #define M4U_PORT_L4_VDEC_UFO_EXT        MTK_M4U_ID(4, 1)
0058 #define M4U_PORT_L4_VDEC_PP_EXT         MTK_M4U_ID(4, 2)
0059 #define M4U_PORT_L4_VDEC_PRED_RD_EXT        MTK_M4U_ID(4, 3)
0060 #define M4U_PORT_L4_VDEC_PRED_WR_EXT        MTK_M4U_ID(4, 4)
0061 #define M4U_PORT_L4_VDEC_PPWRAP_EXT     MTK_M4U_ID(4, 5)
0062 #define M4U_PORT_L4_VDEC_TILE_EXT       MTK_M4U_ID(4, 6)
0063 #define M4U_PORT_L4_VDEC_VLD_EXT        MTK_M4U_ID(4, 7)
0064 #define M4U_PORT_L4_VDEC_VLD2_EXT       MTK_M4U_ID(4, 8)
0065 #define M4U_PORT_L4_VDEC_AVC_MV_EXT     MTK_M4U_ID(4, 9)
0066 #define M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT    MTK_M4U_ID(4, 10)
0067
0068 /* larb5 */
0069 #define M4U_PORT_L5_VDEC_LAT0_VLD_EXT       MTK_M4U_ID(5, 0)
0070 #define M4U_PORT_L5_VDEC_LAT0_VLD2_EXT      MTK_M4U_ID(5, 1)
0071 #define M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT    MTK_M4U_ID(5, 2)
0072 #define M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT   MTK_M4U_ID(5, 3)
0073 #define M4U_PORT_L5_VDEC_LAT0_TILE_EXT      MTK_M4U_ID(5, 4)
0074 #define M4U_PORT_L5_VDEC_LAT0_WDMA_EXT      MTK_M4U_ID(5, 5)
0075 #define M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT   MTK_M4U_ID(5, 6)
0076 #define M4U_PORT_L5_VDEC_UFO_ENC_EXT        MTK_M4U_ID(5, 7)
0077
0078 /* larb6: null */
0079
0080 /* larb7 */
0081 #define M4U_PORT_L7_VENC_RCPU           MTK_M4U_ID(7, 0)
0082 #define M4U_PORT_L7_VENC_REC            MTK_M4U_ID(7, 1)
0083 #define M4U_PORT_L7_VENC_BSDMA          MTK_M4U_ID(7, 2)
0084 #define M4U_PORT_L7_VENC_SV_COMV        MTK_M4U_ID(7, 3)
0085 #define M4U_PORT_L7_VENC_RD_COMV        MTK_M4U_ID(7, 4)
0086 #define M4U_PORT_L7_VENC_CUR_LUMA       MTK_M4U_ID(7, 5)
0087 #define M4U_PORT_L7_VENC_CUR_CHROMA     MTK_M4U_ID(7, 6)
0088 #define M4U_PORT_L7_VENC_REF_LUMA       MTK_M4U_ID(7, 7)
0089 #define M4U_PORT_L7_VENC_REF_CHROMA     MTK_M4U_ID(7, 8)
0090 #define M4U_PORT_L7_JPGENC_Y_RDMA       MTK_M4U_ID(7, 9)
0091 #define M4U_PORT_L7_JPGENC_Q_RDMA       MTK_M4U_ID(7, 10)
0092 #define M4U_PORT_L7_JPGENC_C_TABLE      MTK_M4U_ID(7, 11)
0093 #define M4U_PORT_L7_JPGENC_BSDMA        MTK_M4U_ID(7, 12)
0094 #define M4U_PORT_L7_VENC_SUB_R_LUMA     MTK_M4U_ID(7, 13)
0095 #define M4U_PORT_L7_VENC_SUB_W_LUMA     MTK_M4U_ID(7, 14)
0096
0097 /* larb8: null */
0098
0099 /* larb9 */
0100 #define M4U_PORT_L9_IMG_IMGI_D1         MTK_M4U_ID(9, 0)
0101 #define M4U_PORT_L9_IMG_IMGBI_D1        MTK_M4U_ID(9, 1)
0102 #define M4U_PORT_L9_IMG_DMGI_D1         MTK_M4U_ID(9, 2)
0103 #define M4U_PORT_L9_IMG_DEPI_D1         MTK_M4U_ID(9, 3)
0104 #define M4U_PORT_L9_IMG_ICE_D1          MTK_M4U_ID(9, 4)
0105 #define M4U_PORT_L9_IMG_SMTI_D1         MTK_M4U_ID(9, 5)
0106 #define M4U_PORT_L9_IMG_SMTO_D2         MTK_M4U_ID(9, 6)
0107 #define M4U_PORT_L9_IMG_SMTO_D1         MTK_M4U_ID(9, 7)
0108 #define M4U_PORT_L9_IMG_CRZO_D1         MTK_M4U_ID(9, 8)
0109 #define M4U_PORT_L9_IMG_IMG3O_D1        MTK_M4U_ID(9, 9)
0110 #define M4U_PORT_L9_IMG_VIPI_D1         MTK_M4U_ID(9, 10)
0111 #define M4U_PORT_L9_IMG_SMTI_D5         MTK_M4U_ID(9, 11)
0112 #define M4U_PORT_L9_IMG_TIMGO_D1        MTK_M4U_ID(9, 12)
0113 #define M4U_PORT_L9_IMG_UFBC_W0         MTK_M4U_ID(9, 13)
0114 #define M4U_PORT_L9_IMG_UFBC_R0         MTK_M4U_ID(9, 14)
0115
0116 /* larb10: null */
0117
0118 /* larb11 */
0119 #define M4U_PORT_L11_IMG_IMGI_D1        MTK_M4U_ID(11, 0)
0120 #define M4U_PORT_L11_IMG_IMGBI_D1       MTK_M4U_ID(11, 1)
0121 #define M4U_PORT_L11_IMG_DMGI_D1        MTK_M4U_ID(11, 2)
0122 #define M4U_PORT_L11_IMG_DEPI_D1        MTK_M4U_ID(11, 3)
0123 #define M4U_PORT_L11_IMG_ICE_D1         MTK_M4U_ID(11, 4)
0124 #define M4U_PORT_L11_IMG_SMTI_D1        MTK_M4U_ID(11, 5)
0125 #define M4U_PORT_L11_IMG_SMTO_D2        MTK_M4U_ID(11, 6)
0126 #define M4U_PORT_L11_IMG_SMTO_D1        MTK_M4U_ID(11, 7)
0127 #define M4U_PORT_L11_IMG_CRZO_D1        MTK_M4U_ID(11, 8)
0128 #define M4U_PORT_L11_IMG_IMG3O_D1       MTK_M4U_ID(11, 9)
0129 #define M4U_PORT_L11_IMG_VIPI_D1        MTK_M4U_ID(11, 10)
0130 #define M4U_PORT_L11_IMG_SMTI_D5        MTK_M4U_ID(11, 11)
0131 #define M4U_PORT_L11_IMG_TIMGO_D1       MTK_M4U_ID(11, 12)
0132 #define M4U_PORT_L11_IMG_UFBC_W0        MTK_M4U_ID(11, 13)
0133 #define M4U_PORT_L11_IMG_UFBC_R0        MTK_M4U_ID(11, 14)
0134 #define M4U_PORT_L11_IMG_WPE_RDMA1      MTK_M4U_ID(11, 15)
0135 #define M4U_PORT_L11_IMG_WPE_RDMA0      MTK_M4U_ID(11, 16)
0136 #define M4U_PORT_L11_IMG_WPE_WDMA       MTK_M4U_ID(11, 17)
0137 #define M4U_PORT_L11_IMG_MFB_RDMA0      MTK_M4U_ID(11, 18)
0138 #define M4U_PORT_L11_IMG_MFB_RDMA1      MTK_M4U_ID(11, 19)
0139 #define M4U_PORT_L11_IMG_MFB_RDMA2      MTK_M4U_ID(11, 20)
0140 #define M4U_PORT_L11_IMG_MFB_RDMA3      MTK_M4U_ID(11, 21)
0141 #define M4U_PORT_L11_IMG_MFB_RDMA4      MTK_M4U_ID(11, 22)
0142 #define M4U_PORT_L11_IMG_MFB_RDMA5      MTK_M4U_ID(11, 23)
0143 #define M4U_PORT_L11_IMG_MFB_WDMA0      MTK_M4U_ID(11, 24)
0144 #define M4U_PORT_L11_IMG_MFB_WDMA1      MTK_M4U_ID(11, 25)
0145
0146 /* larb12: null */
0147
0148 /* larb13 */
0149 #define M4U_PORT_L13_CAM_MRAWI          MTK_M4U_ID(13, 0)
0150 #define M4U_PORT_L13_CAM_MRAWO0         MTK_M4U_ID(13, 1)
0151 #define M4U_PORT_L13_CAM_MRAWO1         MTK_M4U_ID(13, 2)
0152 #define M4U_PORT_L13_CAM_CAMSV1         MTK_M4U_ID(13, 3)
0153 #define M4U_PORT_L13_CAM_CAMSV2         MTK_M4U_ID(13, 4)
0154 #define M4U_PORT_L13_CAM_CAMSV3         MTK_M4U_ID(13, 5)
0155 #define M4U_PORT_L13_CAM_CAMSV4         MTK_M4U_ID(13, 6)
0156 #define M4U_PORT_L13_CAM_CAMSV5         MTK_M4U_ID(13, 7)
0157 #define M4U_PORT_L13_CAM_CAMSV6         MTK_M4U_ID(13, 8)
0158 #define M4U_PORT_L13_CAM_CCUI           MTK_M4U_ID(13, 9)
0159 #define M4U_PORT_L13_CAM_CCUO           MTK_M4U_ID(13, 10)
0160 #define M4U_PORT_L13_CAM_FAKE           MTK_M4U_ID(13, 11)
0161
0162 /* larb14 */
0163 #define M4U_PORT_L14_CAM_RESERVE1       MTK_M4U_ID(14, 0)
0164 #define M4U_PORT_L14_CAM_RESERVE2       MTK_M4U_ID(14, 1)
0165 #define M4U_PORT_L14_CAM_RESERVE3       MTK_M4U_ID(14, 2)
0166 #define M4U_PORT_L14_CAM_CAMSV0         MTK_M4U_ID(14, 3)
0167 #define M4U_PORT_L14_CAM_CCUI           MTK_M4U_ID(14, 4)
0168 #define M4U_PORT_L14_CAM_CCUO           MTK_M4U_ID(14, 5)
0169
0170 /* larb15: null */
0171
0172 /* larb16 */
0173 #define M4U_PORT_L16_CAM_IMGO_R1_A      MTK_M4U_ID(16, 0)
0174 #define M4U_PORT_L16_CAM_RRZO_R1_A      MTK_M4U_ID(16, 1)
0175 #define M4U_PORT_L16_CAM_CQI_R1_A       MTK_M4U_ID(16, 2)
0176 #define M4U_PORT_L16_CAM_BPCI_R1_A      MTK_M4U_ID(16, 3)
0177 #define M4U_PORT_L16_CAM_YUVO_R1_A      MTK_M4U_ID(16, 4)
0178 #define M4U_PORT_L16_CAM_UFDI_R2_A      MTK_M4U_ID(16, 5)
0179 #define M4U_PORT_L16_CAM_RAWI_R2_A      MTK_M4U_ID(16, 6)
0180 #define M4U_PORT_L16_CAM_RAWI_R3_A      MTK_M4U_ID(16, 7)
0181 #define M4U_PORT_L16_CAM_AAO_R1_A       MTK_M4U_ID(16, 8)
0182 #define M4U_PORT_L16_CAM_AFO_R1_A       MTK_M4U_ID(16, 9)
0183 #define M4U_PORT_L16_CAM_FLKO_R1_A      MTK_M4U_ID(16, 10)
0184 #define M4U_PORT_L16_CAM_LCESO_R1_A     MTK_M4U_ID(16, 11)
0185 #define M4U_PORT_L16_CAM_CRZO_R1_A      MTK_M4U_ID(16, 12)
0186 #define M4U_PORT_L16_CAM_LTMSO_R1_A     MTK_M4U_ID(16, 13)
0187 #define M4U_PORT_L16_CAM_RSSO_R1_A      MTK_M4U_ID(16, 14)
0188 #define M4U_PORT_L16_CAM_AAHO_R1_A      MTK_M4U_ID(16, 15)
0189 #define M4U_PORT_L16_CAM_LSCI_R1_A      MTK_M4U_ID(16, 16)
0190
0191 /* larb17 */
0192 #define M4U_PORT_L17_CAM_IMGO_R1_B      MTK_M4U_ID(17, 0)
0193 #define M4U_PORT_L17_CAM_RRZO_R1_B      MTK_M4U_ID(17, 1)
0194 #define M4U_PORT_L17_CAM_CQI_R1_B       MTK_M4U_ID(17, 2)
0195 #define M4U_PORT_L17_CAM_BPCI_R1_B      MTK_M4U_ID(17, 3)
0196 #define M4U_PORT_L17_CAM_YUVO_R1_B      MTK_M4U_ID(17, 4)
0197 #define M4U_PORT_L17_CAM_UFDI_R2_B      MTK_M4U_ID(17, 5)
0198 #define M4U_PORT_L17_CAM_RAWI_R2_B      MTK_M4U_ID(17, 6)
0199 #define M4U_PORT_L17_CAM_RAWI_R3_B      MTK_M4U_ID(17, 7)
0200 #define M4U_PORT_L17_CAM_AAO_R1_B       MTK_M4U_ID(17, 8)
0201 #define M4U_PORT_L17_CAM_AFO_R1_B       MTK_M4U_ID(17, 9)
0202 #define M4U_PORT_L17_CAM_FLKO_R1_B      MTK_M4U_ID(17, 10)
0203 #define M4U_PORT_L17_CAM_LCESO_R1_B     MTK_M4U_ID(17, 11)
0204 #define M4U_PORT_L17_CAM_CRZO_R1_B      MTK_M4U_ID(17, 12)
0205 #define M4U_PORT_L17_CAM_LTMSO_R1_B     MTK_M4U_ID(17, 13)
0206 #define M4U_PORT_L17_CAM_RSSO_R1_B      MTK_M4U_ID(17, 14)
0207 #define M4U_PORT_L17_CAM_AAHO_R1_B      MTK_M4U_ID(17, 15)
0208 #define M4U_PORT_L17_CAM_LSCI_R1_B      MTK_M4U_ID(17, 16)
0209
0210 /* larb18 */
0211 #define M4U_PORT_L18_CAM_IMGO_R1_C      MTK_M4U_ID(18, 0)
0212 #define M4U_PORT_L18_CAM_RRZO_R1_C      MTK_M4U_ID(18, 1)
0213 #define M4U_PORT_L18_CAM_CQI_R1_C       MTK_M4U_ID(18, 2)
0214 #define M4U_PORT_L18_CAM_BPCI_R1_C      MTK_M4U_ID(18, 3)
0215 #define M4U_PORT_L18_CAM_YUVO_R1_C      MTK_M4U_ID(18, 4)
0216 #define M4U_PORT_L18_CAM_UFDI_R2_C      MTK_M4U_ID(18, 5)
0217 #define M4U_PORT_L18_CAM_RAWI_R2_C      MTK_M4U_ID(18, 6)
0218 #define M4U_PORT_L18_CAM_RAWI_R3_C      MTK_M4U_ID(18, 7)
0219 #define M4U_PORT_L18_CAM_AAO_R1_C       MTK_M4U_ID(18, 8)
0220 #define M4U_PORT_L18_CAM_AFO_R1_C       MTK_M4U_ID(18, 9)
0221 #define M4U_PORT_L18_CAM_FLKO_R1_C      MTK_M4U_ID(18, 10)
0222 #define M4U_PORT_L18_CAM_LCESO_R1_C     MTK_M4U_ID(18, 11)
0223 #define M4U_PORT_L18_CAM_CRZO_R1_C      MTK_M4U_ID(18, 12)
0224 #define M4U_PORT_L18_CAM_LTMSO_R1_C     MTK_M4U_ID(18, 13)
0225 #define M4U_PORT_L18_CAM_RSSO_R1_C      MTK_M4U_ID(18, 14)
0226 #define M4U_PORT_L18_CAM_AAHO_R1_C      MTK_M4U_ID(18, 15)
0227 #define M4U_PORT_L18_CAM_LSCI_R1_C      MTK_M4U_ID(18, 16)
0228
0229 /* larb19 */
0230 #define M4U_PORT_L19_IPE_DVS_RDMA       MTK_M4U_ID(19, 0)
0231 #define M4U_PORT_L19_IPE_DVS_WDMA       MTK_M4U_ID(19, 1)
0232 #define M4U_PORT_L19_IPE_DVP_RDMA       MTK_M4U_ID(19, 2)
0233 #define M4U_PORT_L19_IPE_DVP_WDMA       MTK_M4U_ID(19, 3)
0234
0235 /* larb20 */
0236 #define M4U_PORT_L20_IPE_FDVT_RDA       MTK_M4U_ID(20, 0)
0237 #define M4U_PORT_L20_IPE_FDVT_RDB       MTK_M4U_ID(20, 1)
0238 #define M4U_PORT_L20_IPE_FDVT_WRA       MTK_M4U_ID(20, 2)
0239 #define M4U_PORT_L20_IPE_FDVT_WRB       MTK_M4U_ID(20, 3)
0240 #define M4U_PORT_L20_IPE_RSC_RDMA0      MTK_M4U_ID(20, 4)
0241 #define M4U_PORT_L20_IPE_RSC_WDMA       MTK_M4U_ID(20, 5)
0242
0243 #endif