dt-bindings/memory/mt8186-memory-port.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2022 MediaTek Inc.
0004  *
0005  * Author: Anan Sun <anan.sun@mediatek.com>
0006  * Author: Yong Wu <yong.wu@mediatek.com>
0007  */
0008 #ifndef _DT_BINDINGS_MEMORY_MT8186_LARB_PORT_H_
0009 #define _DT_BINDINGS_MEMORY_MT8186_LARB_PORT_H_
0010
0011 #include <dt-bindings/memory/mtk-memory-port.h>
0012
0013 /*
0014  * MM IOMMU supports 16GB dma address. We separate it to four ranges:
0015  * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
0016  * locate in anyone region. BUT:
0017  * a) Make sure all the ports inside a larb are in one range.
0018  * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
0019  *
0020  * This is the suggested mapping in this SoC:
0021  *
0022  * modules    dma-address-region    larbs-ports
0023  * disp         0 ~ 4G                  larb0/1/2
0024  * vcodec      4G ~ 8G                  larb4/7
0025  * cam/mdp     8G ~ 12G                 the other larbs.
0026  * N/A         12G ~ 16G
0027  * CCU0   0x24000_0000 ~ 0x243ff_ffff   larb13: port 9/10
0028  * CCU1   0x24400_0000 ~ 0x247ff_ffff   larb14: port 4/5
0029  */
0030
0031 /* MM IOMMU ports */
0032 /* LARB 0 -- MMSYS */
0033 #define IOMMU_PORT_L0_DISP_POSTMASK0    MTK_M4U_ID(0, 0)
0034 #define IOMMU_PORT_L0_REVERSED      MTK_M4U_ID(0, 1)
0035 #define IOMMU_PORT_L0_OVL_RDMA0     MTK_M4U_ID(0, 2)
0036 #define IOMMU_PORT_L0_DISP_FAKE0    MTK_M4U_ID(0, 3)
0037
0038 /* LARB 1 -- MMSYS */
0039 #define IOMMU_PORT_L1_DISP_RDMA1    MTK_M4U_ID(1, 0)
0040 #define IOMMU_PORT_L1_OVL_2L_RDMA0  MTK_M4U_ID(1, 1)
0041 #define IOMMU_PORT_L1_DISP_RDMA0    MTK_M4U_ID(1, 2)
0042 #define IOMMU_PORT_L1_DISP_WDMA0    MTK_M4U_ID(1, 3)
0043 #define IOMMU_PORT_L1_DISP_FAKE1    MTK_M4U_ID(1, 4)
0044
0045 /* LARB 2 -- MMSYS */
0046 #define IOMMU_PORT_L2_MDP_RDMA0     MTK_M4U_ID(2, 0)
0047 #define IOMMU_PORT_L2_MDP_RDMA1     MTK_M4U_ID(2, 1)
0048 #define IOMMU_PORT_L2_MDP_WROT0     MTK_M4U_ID(2, 2)
0049 #define IOMMU_PORT_L2_MDP_WROT1     MTK_M4U_ID(2, 3)
0050 #define IOMMU_PORT_L2_DISP_FAKE0    MTK_M4U_ID(2, 4)
0051
0052 /* LARB 4 -- VDEC */
0053 #define IOMMU_PORT_L4_HW_VDEC_MC_EXT        MTK_M4U_ID(4, 0)
0054 #define IOMMU_PORT_L4_HW_VDEC_UFO_EXT       MTK_M4U_ID(4, 1)
0055 #define IOMMU_PORT_L4_HW_VDEC_PP_EXT        MTK_M4U_ID(4, 2)
0056 #define IOMMU_PORT_L4_HW_VDEC_PRED_RD_EXT   MTK_M4U_ID(4, 3)
0057 #define IOMMU_PORT_L4_HW_VDEC_PRED_WR_EXT   MTK_M4U_ID(4, 4)
0058 #define IOMMU_PORT_L4_HW_VDEC_PPWRAP_EXT    MTK_M4U_ID(4, 5)
0059 #define IOMMU_PORT_L4_HW_VDEC_TILE_EXT      MTK_M4U_ID(4, 6)
0060 #define IOMMU_PORT_L4_HW_VDEC_VLD_EXT       MTK_M4U_ID(4, 7)
0061 #define IOMMU_PORT_L4_HW_VDEC_VLD2_EXT      MTK_M4U_ID(4, 8)
0062 #define IOMMU_PORT_L4_HW_VDEC_AVC_MV_EXT    MTK_M4U_ID(4, 9)
0063 #define IOMMU_PORT_L4_HW_VDEC_UFO_ENC_EXT   MTK_M4U_ID(4, 10)
0064 #define IOMMU_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT   MTK_M4U_ID(4, 11)
0065 #define IOMMU_PORT_L4_HW_MINI_MDP_R0_EXT    MTK_M4U_ID(4, 12)
0066 #define IOMMU_PORT_L4_HW_MINI_MDP_W0_EXT    MTK_M4U_ID(4, 13)
0067
0068 /* LARB 7 -- VENC */
0069 #define IOMMU_PORT_L7_VENC_RCPU     MTK_M4U_ID(7, 0)
0070 #define IOMMU_PORT_L7_VENC_REC      MTK_M4U_ID(7, 1)
0071 #define IOMMU_PORT_L7_VENC_BSDMA    MTK_M4U_ID(7, 2)
0072 #define IOMMU_PORT_L7_VENC_SV_COMV  MTK_M4U_ID(7, 3)
0073 #define IOMMU_PORT_L7_VENC_RD_COMV  MTK_M4U_ID(7, 4)
0074 #define IOMMU_PORT_L7_VENC_CUR_LUMA MTK_M4U_ID(7, 5)
0075 #define IOMMU_PORT_L7_VENC_CUR_CHROMA   MTK_M4U_ID(7, 6)
0076 #define IOMMU_PORT_L7_VENC_REF_LUMA MTK_M4U_ID(7, 7)
0077 #define IOMMU_PORT_L7_VENC_REF_CHROMA   MTK_M4U_ID(7, 8)
0078 #define IOMMU_PORT_L7_JPGENC_Y_RDMA MTK_M4U_ID(7, 9)
0079 #define IOMMU_PORT_L7_JPGENC_C_RDMA MTK_M4U_ID(7, 10)
0080 #define IOMMU_PORT_L7_JPGENC_Q_TABLE    MTK_M4U_ID(7, 11)
0081 #define IOMMU_PORT_L7_JPGENC_BSDMA  MTK_M4U_ID(7, 12)
0082
0083 /* LARB 8 -- WPE */
0084 #define IOMMU_PORT_L8_WPE_RDMA_0    MTK_M4U_ID(8, 0)
0085 #define IOMMU_PORT_L8_WPE_RDMA_1    MTK_M4U_ID(8, 1)
0086 #define IOMMU_PORT_L8_WPE_WDMA_0    MTK_M4U_ID(8, 2)
0087
0088 /* LARB 9 -- IMG-1 */
0089 #define IOMMU_PORT_L9_IMG_IMGI_D1   MTK_M4U_ID(9, 0)
0090 #define IOMMU_PORT_L9_IMG_IMGBI_D1  MTK_M4U_ID(9, 1)
0091 #define IOMMU_PORT_L9_IMG_DMGI_D1   MTK_M4U_ID(9, 2)
0092 #define IOMMU_PORT_L9_IMG_DEPI_D1   MTK_M4U_ID(9, 3)
0093 #define IOMMU_PORT_L9_IMG_LCE_D1    MTK_M4U_ID(9, 4)
0094 #define IOMMU_PORT_L9_IMG_SMTI_D1   MTK_M4U_ID(9, 5)
0095 #define IOMMU_PORT_L9_IMG_SMTO_D2   MTK_M4U_ID(9, 6)
0096 #define IOMMU_PORT_L9_IMG_SMTO_D1   MTK_M4U_ID(9, 7)
0097 #define IOMMU_PORT_L9_IMG_CRZO_D1   MTK_M4U_ID(9, 8)
0098 #define IOMMU_PORT_L9_IMG_IMG3O_D1  MTK_M4U_ID(9, 9)
0099 #define IOMMU_PORT_L9_IMG_VIPI_D1   MTK_M4U_ID(9, 10)
0100 #define IOMMU_PORT_L9_IMG_SMTI_D5   MTK_M4U_ID(9, 11)
0101 #define IOMMU_PORT_L9_IMG_TIMGO_D1  MTK_M4U_ID(9, 12)
0102 #define IOMMU_PORT_L9_IMG_UFBC_W0   MTK_M4U_ID(9, 13)
0103 #define IOMMU_PORT_L9_IMG_UFBC_R0   MTK_M4U_ID(9, 14)
0104 #define IOMMU_PORT_L9_IMG_WPE_RDMA1 MTK_M4U_ID(9, 15)
0105 #define IOMMU_PORT_L9_IMG_WPE_RDMA0 MTK_M4U_ID(9, 16)
0106 #define IOMMU_PORT_L9_IMG_WPE_WDMA  MTK_M4U_ID(9, 17)
0107 #define IOMMU_PORT_L9_IMG_MFB_RDMA0 MTK_M4U_ID(9, 18)
0108 #define IOMMU_PORT_L9_IMG_MFB_RDMA1 MTK_M4U_ID(9, 19)
0109 #define IOMMU_PORT_L9_IMG_MFB_RDMA2 MTK_M4U_ID(9, 20)
0110 #define IOMMU_PORT_L9_IMG_MFB_RDMA3 MTK_M4U_ID(9, 21)
0111 #define IOMMU_PORT_L9_IMG_MFB_RDMA4 MTK_M4U_ID(9, 22)
0112 #define IOMMU_PORT_L9_IMG_MFB_RDMA5 MTK_M4U_ID(9, 23)
0113 #define IOMMU_PORT_L9_IMG_MFB_WDMA0 MTK_M4U_ID(9, 24)
0114 #define IOMMU_PORT_L9_IMG_MFB_WDMA1 MTK_M4U_ID(9, 25)
0115 #define IOMMU_PORT_L9_IMG_RESERVE6  MTK_M4U_ID(9, 26)
0116 #define IOMMU_PORT_L9_IMG_RESERVE7  MTK_M4U_ID(9, 27)
0117 #define IOMMU_PORT_L9_IMG_RESERVE8  MTK_M4U_ID(9, 28)
0118
0119 /* LARB 11 -- IMG-2 */
0120 #define IOMMU_PORT_L11_IMG_IMGI_D1  MTK_M4U_ID(11, 0)
0121 #define IOMMU_PORT_L11_IMG_IMGBI_D1 MTK_M4U_ID(11, 1)
0122 #define IOMMU_PORT_L11_IMG_DMGI_D1  MTK_M4U_ID(11, 2)
0123 #define IOMMU_PORT_L11_IMG_DEPI_D1  MTK_M4U_ID(11, 3)
0124 #define IOMMU_PORT_L11_IMG_LCE_D1   MTK_M4U_ID(11, 4)
0125 #define IOMMU_PORT_L11_IMG_SMTI_D1  MTK_M4U_ID(11, 5)
0126 #define IOMMU_PORT_L11_IMG_SMTO_D2  MTK_M4U_ID(11, 6)
0127 #define IOMMU_PORT_L11_IMG_SMTO_D1  MTK_M4U_ID(11, 7)
0128 #define IOMMU_PORT_L11_IMG_CRZO_D1  MTK_M4U_ID(11, 8)
0129 #define IOMMU_PORT_L11_IMG_IMG3O_D1 MTK_M4U_ID(11, 9)
0130 #define IOMMU_PORT_L11_IMG_VIPI_D1  MTK_M4U_ID(11, 10)
0131 #define IOMMU_PORT_L11_IMG_SMTI_D5  MTK_M4U_ID(11, 11)
0132 #define IOMMU_PORT_L11_IMG_TIMGO_D1 MTK_M4U_ID(11, 12)
0133 #define IOMMU_PORT_L11_IMG_UFBC_W0  MTK_M4U_ID(11, 13)
0134 #define IOMMU_PORT_L11_IMG_UFBC_R0  MTK_M4U_ID(11, 14)
0135 #define IOMMU_PORT_L11_IMG_WPE_RDMA1    MTK_M4U_ID(11, 15)
0136 #define IOMMU_PORT_L11_IMG_WPE_RDMA0    MTK_M4U_ID(11, 16)
0137 #define IOMMU_PORT_L11_IMG_WPE_WDMA MTK_M4U_ID(11, 17)
0138 #define IOMMU_PORT_L11_IMG_MFB_RDMA0    MTK_M4U_ID(11, 18)
0139 #define IOMMU_PORT_L11_IMG_MFB_RDMA1    MTK_M4U_ID(11, 19)
0140 #define IOMMU_PORT_L11_IMG_MFB_RDMA2    MTK_M4U_ID(11, 20)
0141 #define IOMMU_PORT_L11_IMG_MFB_RDMA3    MTK_M4U_ID(11, 21)
0142 #define IOMMU_PORT_L11_IMG_MFB_RDMA4    MTK_M4U_ID(11, 22)
0143 #define IOMMU_PORT_L11_IMG_MFB_RDMA5    MTK_M4U_ID(11, 23)
0144 #define IOMMU_PORT_L11_IMG_MFB_WDMA0    MTK_M4U_ID(11, 24)
0145 #define IOMMU_PORT_L11_IMG_MFB_WDMA1    MTK_M4U_ID(11, 25)
0146 #define IOMMU_PORT_L11_IMG_RESERVE6 MTK_M4U_ID(11, 26)
0147 #define IOMMU_PORT_L11_IMG_RESERVE7 MTK_M4U_ID(11, 27)
0148 #define IOMMU_PORT_L11_IMG_RESERVE8 MTK_M4U_ID(11, 28)
0149
0150 /* LARB 13 -- CAM */
0151 #define IOMMU_PORT_L13_CAM_MRAWI    MTK_M4U_ID(13, 0)
0152 #define IOMMU_PORT_L13_CAM_MRAWO_0  MTK_M4U_ID(13, 1)
0153 #define IOMMU_PORT_L13_CAM_MRAWO_1  MTK_M4U_ID(13, 2)
0154 #define IOMMU_PORT_L13_CAM_CAMSV_4  MTK_M4U_ID(13, 6)
0155 #define IOMMU_PORT_L13_CAM_CAMSV_5  MTK_M4U_ID(13, 7)
0156 #define IOMMU_PORT_L13_CAM_CAMSV_6  MTK_M4U_ID(13, 8)
0157 #define IOMMU_PORT_L13_CAM_CCUI     MTK_M4U_ID(13, 9)
0158 #define IOMMU_PORT_L13_CAM_CCUO     MTK_M4U_ID(13, 10)
0159 #define IOMMU_PORT_L13_CAM_FAKE     MTK_M4U_ID(13, 11)
0160
0161 /* LARB 14 -- CAM */
0162 #define IOMMU_PORT_L14_CAM_CCUI     MTK_M4U_ID(14, 4)
0163 #define IOMMU_PORT_L14_CAM_CCUO     MTK_M4U_ID(14, 5)
0164
0165 /* LARB 16 -- RAW-A */
0166 #define IOMMU_PORT_L16_CAM_IMGO_R1_A    MTK_M4U_ID(16, 0)
0167 #define IOMMU_PORT_L16_CAM_RRZO_R1_A    MTK_M4U_ID(16, 1)
0168 #define IOMMU_PORT_L16_CAM_CQI_R1_A MTK_M4U_ID(16, 2)
0169 #define IOMMU_PORT_L16_CAM_BPCI_R1_A    MTK_M4U_ID(16, 3)
0170 #define IOMMU_PORT_L16_CAM_YUVO_R1_A    MTK_M4U_ID(16, 4)
0171 #define IOMMU_PORT_L16_CAM_UFDI_R2_A    MTK_M4U_ID(16, 5)
0172 #define IOMMU_PORT_L16_CAM_RAWI_R2_A    MTK_M4U_ID(16, 6)
0173 #define IOMMU_PORT_L16_CAM_RAWI_R3_A    MTK_M4U_ID(16, 7)
0174 #define IOMMU_PORT_L16_CAM_AAO_R1_A MTK_M4U_ID(16, 8)
0175 #define IOMMU_PORT_L16_CAM_AFO_R1_A MTK_M4U_ID(16, 9)
0176 #define IOMMU_PORT_L16_CAM_FLKO_R1_A    MTK_M4U_ID(16, 10)
0177 #define IOMMU_PORT_L16_CAM_LCESO_R1_A   MTK_M4U_ID(16, 11)
0178 #define IOMMU_PORT_L16_CAM_CRZO_R1_A    MTK_M4U_ID(16, 12)
0179 #define IOMMU_PORT_L16_CAM_LTMSO_R1_A   MTK_M4U_ID(16, 13)
0180 #define IOMMU_PORT_L16_CAM_RSSO_R1_A    MTK_M4U_ID(16, 14)
0181 #define IOMMU_PORT_L16_CAM_AAHO_R1_A    MTK_M4U_ID(16, 15)
0182 #define IOMMU_PORT_L16_CAM_LSCI_R1_A    MTK_M4U_ID(16, 16)
0183
0184 /* LARB 17 -- RAW-B */
0185 #define IOMMU_PORT_L17_CAM_IMGO_R1_B    MTK_M4U_ID(17, 0)
0186 #define IOMMU_PORT_L17_CAM_RRZO_R1_B    MTK_M4U_ID(17, 1)
0187 #define IOMMU_PORT_L17_CAM_CQI_R1_B MTK_M4U_ID(17, 2)
0188 #define IOMMU_PORT_L17_CAM_BPCI_R1_B    MTK_M4U_ID(17, 3)
0189 #define IOMMU_PORT_L17_CAM_YUVO_R1_B    MTK_M4U_ID(17, 4)
0190 #define IOMMU_PORT_L17_CAM_UFDI_R2_B    MTK_M4U_ID(17, 5)
0191 #define IOMMU_PORT_L17_CAM_RAWI_R2_B    MTK_M4U_ID(17, 6)
0192 #define IOMMU_PORT_L17_CAM_RAWI_R3_B    MTK_M4U_ID(17, 7)
0193 #define IOMMU_PORT_L17_CAM_AAO_R1_B MTK_M4U_ID(17, 8)
0194 #define IOMMU_PORT_L17_CAM_AFO_R1_B MTK_M4U_ID(17, 9)
0195 #define IOMMU_PORT_L17_CAM_FLKO_R1_B    MTK_M4U_ID(17, 10)
0196 #define IOMMU_PORT_L17_CAM_LCESO_R1_B   MTK_M4U_ID(17, 11)
0197 #define IOMMU_PORT_L17_CAM_CRZO_R1_B    MTK_M4U_ID(17, 12)
0198 #define IOMMU_PORT_L17_CAM_LTMSO_R1_B   MTK_M4U_ID(17, 13)
0199 #define IOMMU_PORT_L17_CAM_RSSO_R1_B    MTK_M4U_ID(17, 14)
0200 #define IOMMU_PORT_L17_CAM_AAHO_R1_B    MTK_M4U_ID(17, 15)
0201 #define IOMMU_PORT_L17_CAM_LSCI_R1_B    MTK_M4U_ID(17, 16)
0202
0203 /* LARB 19 -- IPE */
0204 #define IOMMU_PORT_L19_IPE_DVS_RDMA MTK_M4U_ID(19, 0)
0205 #define IOMMU_PORT_L19_IPE_DVS_WDMA MTK_M4U_ID(19, 1)
0206 #define IOMMU_PORT_L19_IPE_DVP_RDMA MTK_M4U_ID(19, 2)
0207 #define IOMMU_PORT_L19_IPE_DVP_WDMA MTK_M4U_ID(19, 3)
0208
0209 /* LARB 20 -- IPE */
0210 #define IOMMU_PORT_L20_IPE_FDVT_RDA MTK_M4U_ID(20, 0)
0211 #define IOMMU_PORT_L20_IPE_FDVT_RDB MTK_M4U_ID(20, 1)
0212 #define IOMMU_PORT_L20_IPE_FDVT_WRA MTK_M4U_ID(20, 2)
0213 #define IOMMU_PORT_L20_IPE_FDVT_WRB MTK_M4U_ID(20, 3)
0214 #define IOMMU_PORT_L20_IPE_RSC_RDMA0    MTK_M4U_ID(20, 4)
0215 #define IOMMU_PORT_L20_IPE_RSC_WDMA MTK_M4U_ID(20, 5)
0216
0217 #endif